Selective real-time cryptography in a vehicle communication network

US11722293B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11722293-B2
Application numberUS-202217684670-A
CountryUS
Kind codeB2
Filing dateMar 2, 2022
Priority dateJan 25, 2019
Publication dateAug 8, 2023
Grant dateAug 8, 2023

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A sender device includes: a first sequence generator configured to generate a first sequence of bits having a bit pattern that incudes first bit values and second bit values; a first parsing processor configured to receive a first plurality of data blocks and the first sequence of bits, and select a first subset of data blocks and a second subset of data blocks from the first plurality of data blocks based on the bit pattern; an encryption processor configured to encrypt the selected first subset of data blocks received from the first parsing processor to generate encrypted data blocks and output the encrypted data blocks to an output terminal that is configured to output the encrypted data blocks and the selected second subset of data blocks as unencrypted data blocks from the sender device.

First claim

Opening claim text (preview).

What is claimed is: 1. A communication system, comprising: a sender device configured to send a first plurality of data blocks, the sender device comprising: a first sequence generator configured to generate a first sequence of bits having a bit pattern, wherein the first sequence generator is configured to generate the first sequence of bits independent of the first plurality of data blocks, wherein the first sequence of bits comprises first bits each having a first bit value and second bits each having a second bit value different from the first bit value, wherein the first bits and the second bits are arranged according to the bit pattern; a first parsing processor configured to receive the first plurality of data blocks and the first sequence of bits, select a first subset of data blocks from the first plurality of data blocks based on the bit pattern, select a second subset of data blocks from the first plurality of data blocks based on the bit pattern, output the selected first subset of data blocks to a first signal path, and output the selected second subset of data blocks to a second signal path coupled to an output terminal; and an encryption processor configured to encrypt the selected first subset of data blocks received from the first parsing processor to generate encrypted data blocks and output the encrypted data blocks to the output terminal, wherein the second signal path bypasses the encryption processor such that the selected second subset of data blocks remain unencrypted data blocks, and wherein the output terminal is configured to output the encrypted data blocks and the unencrypted data blocks from the sender device. 2. The communication system of claim 1 , wherein the first parsing processor is configured to associate each data block of the first plurality of data blocks to a different corresponding bit of the first sequence of bits, select data blocks from the first plurality of data blocks that are associated with the first bits of the first sequence of bits having the first bit value to be used as the selected first subset of data blocks, and select data blocks from the first plurality of data blocks that are associated with the second bits of the first sequence of bits having the second bit value to be used as the selected second subset of data blocks. 3. The communication system of claim 1 , wherein the first sequence generator is a random sequence generator, the first sequence of bits is a random bit sequence, and the bit pattern is a randomized bit pattern comprising a randomized intermixing of the first bit values and the second bit values. 4. The communication system of claim 1 , wherein the sender device further comprises: a memory configured to store the first plurality of data blocks. 5. The communication system of claim 1 , wherein the encryption processor is configured to encrypt each data block of the selected first subset of data blocks into ciphertext. 6. The communication system of claim 5 , wherein each data block of the selected second subset of data blocks is output from the output terminal as plaintext. 7. The communication system of claim 1 , wherein the output terminal is configured to output the encrypted data blocks and the unencrypted data blocks from the sender device in a single data stream. 8. The communication system of claim 1 , wherein: in response to the communication system being powered on, the first sequence generator is configured to generate a different sequence of bits representative of a different bit pattern, wherein the first sequence generator is configured to change the first sequence of bits to the different sequence of bits to create the different bit pattern, wherein the different sequence of bits comprises third bits each having the first bit value and fourth bits each having the second bit value, wherein the third bits and the fourth bits are arranged according to the different bit pattern, wherein the first parsing processor is configured to receive a second plurality of data blocks and the different sequence of bits, select a third subset of data blocks from the second plurality of data blocks based on the different bit pattern, select a fourth subset of data blocks from the second plurality of data blocks based on the different bit pattern, output the selected third subset of data blocks to the first signal path, and output the selected fourth subset of data blocks to the second signal path coupled to the output terminal, wherein the first sequence generator is configured to generate the different sequence of bits independent of the second plurality of data blocks, wherein the encryption processor is configured to encrypt the selected third subset of data blocks received from the first parsing processor to generate further encrypted data blocks and output the further encrypted data blocks to the output terminal, wherein the second signal path bypasses the encryption processor such that the selected fourth subset of data blocks remain unencrypted data blocks, and wherein the output terminal is configured to output the further encrypted data blocks and the selected fourth subset of data blocks from the sender device. 9. The communication system of claim 1 , further comprising: a receiver device configured to receive the first plurality of data blocks, which include the encrypted data blocks and the unencrypted data blocks, from the sender device, the receiver device comprising: a second sequence generator configured to generate the first sequence of bits with the bit pattern matching the bit pattern generated by the first sequence generator; a second parsing processor configured to receive the encrypted data blocks and the unencrypted data blocks, receive the first sequence of bits from the second sequence generator, and parse out the encrypted data blocks from the unencrypted data blocks based on the bit pattern; and a decryption processor configured to receive the encrypted data blocks parsed out by the second parsing processor and decrypt the encrypted data blocks. 10. The communication system of claim 9 , wherein the second parsing processor is configured to associate each data block of the first plurality of data blocks to a different corresponding bit of the first sequence of bits, select data blocks from the first plurality of data blocks that are associated with the first bits of the first sequence of bits having the first bit value as the encrypted data blocks to be decrypted by the decryption processor, and select data blocks from the first plurality of data blocks that are associated with the second bits of the first sequence of bits having the second bit values as the unencrypted data blocks. 11. The communication system of claim 9 , wherein: the sender device further comprises a first controller, the receiver device further comprises a second controller, and the first controller and the second controller are configured to synchronize the first sequence generator and the second sequence generator such that the first sequence generator and the second sequence generator generate the first sequence of bits. 12. The communication system of claim 1 , wherein the sender device is further configured to receive a second plurality of data blocks, including second encrypted data blocks and second unencrypted data blocks, wherein the first sequence generator is configured to generate a second sequence of bits having a second bit pattern, wherein the second sequence of bits comprises third bits each having the first bit value and fourth bits each having the second bit value, wherein the third bits and the fourth bits are arranged according to the second bit pattern, wherein the first

Assignees

Inventors

Classifications

  • H04L9/0643Primary

    Hash functions, e.g. MD5, SHA, HMAC or f9 MAC · CPC title

  • with particular pseudorandom sequence generator · CPC title

  • involving negotiation or determination of the one or more network security mechanisms to be used, e.g. by negotiation between the client and the server or between peers or by selection according to the capabilities of the entities involved (negotiation of communication capabilities H04L69/24) · CPC title

  • Vehicles · CPC title

  • H04W12/106Primary

    Packet or message integrity · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US11722293B2 cover?
A sender device includes: a first sequence generator configured to generate a first sequence of bits having a bit pattern that incudes first bit values and second bit values; a first parsing processor configured to receive a first plurality of data blocks and the first sequence of bits, and select a first subset of data blocks and a second subset of data blocks from the first plurality of data …
Who is the assignee on this patent?
Infineon Technologies Ag
What technology area does this patent fall under?
Primary CPC classification H04L9/0643. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 08 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).