Correction of bit errors

Patent metadata

Field	Value
Publication number	US-11722153-B2
Application number	US-202217579721-A
Country	US
Kind code	B2
Filing date	Jan 20, 2022
Priority date	Jan 20, 2021
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

Processing of a bit sequence is proposed, wherein (i) a first partial error syndrome s 1 of an error syndrome and a second partial error syndrome s 2 of the error syndrome are determined for the bit sequence, (ii) a first comparison value is determined on the basis of a bit position and the first partial error syndrome, (iii) a second comparison value is determined on the basis of the bit position and the second partial error syndrome, and (iv) the bit position is corrected should a comparison of the first comparison value with the second comparison value assume a specified value and otherwise the bit position is not corrected.

First claim

What is claimed is:

1. A computer implemented method for processing a bit sequence in a device comprising a first hardware comparison value generator and a second hardware comparison value generator, the computer implemented method comprising:
providing an error syndrome for the bit sequence, the error syndrome having an error syndrome bit length,
determining a first partial error syndrome of the error syndrome, the first partial error syndrome having a first bit length less than the error syndrome bit length,
determining a second partial error syndrome of the error syndrome, the second partial error syndrome having a second bit length less than the error syndrome bit length,
in the first hardware comparison value generator, determining a first comparison value based on a bit position in the bit sequence and the first partial error syndrome,
in a second hardware comparison value generator, determining a second comparison value based on the bit position and the second partial error syndrome, and
changing a bit value at the bit position to a corrected bit value only when a comparison of the first comparison value with the second comparison value is a specified value, and otherwise leaving the bit value at the bit position.

2. The computer implemented method of claim 1 , wherein the changing of the bit value to the corrected bit value uses an error code capable of correcting at least a 2-bit error.

3. The computer implemented method of claim 2 , wherein the error code is a Bose-Chaudhuri-Hocquenghem (BCH) code.

4. The computer implemented method of claim 1 , wherein the bit value is changed to the corrected bit value when the first comparison value equals the second comparison value.

5. The computer implemented method of claim 1 , wherein the first partial error syndrome s 1 and the second partial error syndrome s 2 each have m components of the error syndrome and m>2.

6. The computer implemented method of claim 1 ,
wherein the bit value is assigned a value β, the first partial error syndrome is assigned s 1 , and the second partial error syndrome is assigned s 2 ,
wherein the first comparison value is determined as (s 1 +β) k and the second comparison value is determined as s 2 +β k ,
wherein k≠0, and s 1 , s 2 and β are elements of a Galois field.

7. The computer implemented method of claim 6 , wherein the Galois field is GF(2 m )and m>2.

8. The computer implemented method of claim 6 ,
wherein r bit positions i 0 , i 1 , . . . , i r−1 of the bit sequence are assigned r values α i 0 , α i 1 , α i 2 , α i r−1 ,
wherein first comparison values

[

s
1

+

α

i
0

]

k

,

⁢

[

s
1

+

α

i
1

]

k

,

⁢

[

s
1

+

α

i
2

]

k

,

⁢

⋮
⁢

[

s
1

+

α

i

r
-
1

]

k

and second comparison values

s
2

+

[

α

i
0

]

k

,

⁢

s
2

+

[

α

i
1

]

k

,

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s
2

+

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α

i
2

]

k

,

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⋮

s
2

+

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α

i

r
-
1

]

k

are determined for bit positions to be corrected,
wherein r≥1 and a is a generator of the Galois field.

9. The computer implemented method of claim 6 , wherein k=3 or k=−1.

10. The computer implemented method of claim 1 for error correction of a 2-bit error at bit positions i and j,
wherein the first partial error syndrome is assigned s 1 and is determined as
i s 1 =α i +α j

Assignees

• Infineon Technologies Ag

Inventors

• Kern Thomas
• Goessel Michael
• Rabenalt Thomas

Classifications

• H03M13/1575 Primary

  Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance · CPC title

• H03M13/152 Primary

  Bose-Chaudhuri-Hocquenghem [BCH] codes · CPC title

• H03M13/618

  Shortening and extension of codes · CPC title