Semiconductor device

Patent metadata

Field	Value
Publication number	US-11721750-B2
Application number	US-202117399580-A
Country	US
Kind code	B2
Filing date	Aug 11, 2021
Priority date	Mar 11, 2021
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

A semiconductor device includes a semiconductor part, first and second electrodes, and a control electrode. The semiconductor part is provided between the first and second electrodes. The semiconductor part includes first to seventh layers. The second of a second conductivity type is provided between the first layer of a first conductivity type and the first electrode. The third and fourth layers of the first conductivity type are arranged along the second layer between the second layer and the first electrode. The fifth layer of the second conductivity type is provided between the second electrode and the first layer. The sixth and seventh layers are arranged along the fifth layer between the first and fifth layers. The sixth and seventh layers include the first-conductivity-type impurities with first and second surface densities, respectively. The first surface density is greater than the second surface density.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor part including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, at least one fourth semiconductor layer of the second conductivity type, a fifth semiconductor layer of the second conductivity type, at least one sixth semiconductor layer of the first conductivity type, a seventh semiconductor layer of the first conductivity type, the semiconductor part having a first surface and a second surface at a side opposite to the first surface;
a first electrode provided on the first surface of the semiconductor part, the second semiconductor layer being provided between the first semiconductor layer and the first electrode, the third and fourth semiconductor layers being provided between the second semiconductor layer and the first electrode, the first electrode being electrically connected to the third and fourth semiconductor layers, the third and fourth semiconductor layers being arranged along the first surface of the semiconductor part;
a second electrode provided on the second surface of the semiconductor part, the semiconductor part being provided between the first electrode and the second electrode, the first semiconductor layer extending between the first electrode and the second electrode, the fifth semiconductor layer being provided between the second electrode and the first semiconductor layer, the fifth semiconductor layer being electrically connected to the second electrode, the sixth and seventh semiconductor layers being provided between the first and fifth semiconductor layers, the sixth and seventh semiconductor layers being arranged along the fifth semiconductor layer, the sixth and seventh semiconductor layers including a first-conductivity-type impurity with higher concentrations than a concentration of a first-conductivity-type impurity in the first semiconductor layer, the sixth semiconductor layer including the first-conductivity-type impurity with a first surface density in a plane parallel to the second surface, the seventh semiconductor layer including the first-conductivity-type impurity with a second surface density in the plane parallel to the second surface, the first surface density being greater than the second surface density, the seventh semiconductor layer being provided between two adjacent portions of the sixth semiconductor layer, or between the sixth semiconductor layer and another sixth semiconductor layer; and
at least one control electrode provided between the semiconductor part and the first electrode, the control electrode being electrically insulated from the semiconductor part by a first insulating film and electrically insulated from the first electrode by a second insulating film, the control electrode facing the first and second semiconductor layers via the first insulating film, the first to third semiconductor layers being arranged along the first insulating film.

2. The device according to claim 1 , wherein
the seventh semiconductor layer has a layer thickness in a first direction, the first direction being from the second electrode toward the first electrode, the layer thickness of the seventh semiconductor layer being less than a layer thickness of the sixth semiconductor layer in the first direction.

3. The device according to claim 1 , wherein
the semiconductor part has a first-conductivity-type impurity distribution in a first direction, the first direction being from the second electrode toward the first electrode, and
the first-conductivity-type impurity distribution of the semiconductor part includes a first peak concentration in the sixth semiconductor layer and a second peak concentration in the seventh semiconductor layer, the second peak concentration being greater than the first peak concentration.

4. The device according to claim 1 , wherein
the semiconductor part includes an active region and a termination region in a plane parallel to the first surface, the active region including the second semiconductor layer, the termination region surrounding the active region, and
the seventh semiconductor layer is provided in the active region when viewed along a direction perpendicular to the first surface.

5. The device according to claim 4 , wherein
the seventh semiconductor layer is provided along a boundary between the active region and the termination region when viewed along the direction perpendicular to the first surface.

6. The device according to claim 1 , wherein
the control electrode is provided inside a trench extending from the first surface of the semiconductor part into the first semiconductor layer.

7. The device according to claim 6 , further comprising:
a third electrode provided inside another trench extending from the first surface of the semiconductor part into the first semiconductor layer.

8. The device according to claim 1 , wherein
the control electrode is provided between the first electrode and the sixth semiconductor layer, and the control electrode is not provided between the first electrode and the seventh semiconductor layer.

9. The device according to claim 1 , further comprising:
a plurality of control terminals electrically connected to a plurality of the control electrodes, the control terminals including first and second control terminals, the control electrodes including the first to third control electrode, the first control electrode being provided between the first electrode and the sixth semiconductor layer, the second control electrode being provided between the first electrode and the seventh semiconductor layer, the third control electrode being provided between the first electrode and the seventh semiconductor layer, wherein
the first control terminal is electrically connected to the first and second control electrodes; and the second control terminal is electrically connected to the third control electrode.

10. The device according to claim 9 , wherein
the third control electrode is provided at a position adjacent to the second control electrode.

11. The device according to claim 1 , further comprising:
a fourth electrode provided on the first surface of the semiconductor part, the fourth electrode being apart from the first electrode, the fourth electrode being provided at a position overlapping the seventh semiconductor layer in a first direction, the first direction being from the second electrode toward the first electrode, wherein
the semiconductor part further includes another third semiconductor layer electrically connected to the fourth electrode, and
a plurality of the control electrodes are provided, the control electrodes including first and second control electrode, the first control electrode being provided between the first electrode and the sixth semiconductor layer, the second control electrode being provided between the first electrode and the seventh semiconductor layer, said another third semiconductor layer being next to the second control electrode.

12. The device according to claim 1 , wherein
a plurality of the control electrodes are provided, the control electrodes including first and second control electrode, the first control electrode being provided between the first electrode and the sixth semiconductor layer, the second control electrode being provided between the first electrode and the seventh semiconductor layer, and
the second control electrode has a higher thermal conductivity than a thermal conductivity of the first control electrode.

13. The device according to claim 12 , wherein the first control electr

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Suwa Takeshi
• Matsudai Tomoko
• Iwakaji Yoko
• Itokazu Hiroko

Classifications

• H10D64/232

  Emitter electrodes for IGBTs · CPC title

• H10D64/231

  Emitter or collector electrodes for bipolar transistors · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D12/481 Primary

  having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title