Managing host input/output in a memory system executing a table flush

Patent metadata

Field	Value
Publication number	US-11720490-B2
Application number	US-202117446519-A
Country	US
Kind code	B2
Filing date	Aug 31, 2021
Priority date	Aug 31, 2021
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

Responsive to receiving a table flush command, a first portion of an address mapping table is identified. A first flush operation with respect to a first portion of the address mapping table is performed. Responsive to receiving at least one memory access command, flush operations for a subsequent portion of the address mapping table is suspended. At least one memory access operation specified by the at least one memory access command is performed. A second flush operation with respect to the subsequent portion of the address mapping table is performed.

First claim

What is claimed is:

1. A method comprising:
responsive to receiving a table flush command,
performing a flush operation on the address mapping table;
responsive to receiving at least one memory access command, suspending the flush operation after a predefined portion of the address mapping table is flushed;
performing at least one memory access operation specified by the at least one memory access command; and
resuming the performance of the flush operation on the address mapping table.

2. The method of claim 1 , wherein performing the flush operation includes reading the address mapping table from a volatile memory device and writing the address mapping table to a non-volatile memory device.

3. The method of claim 1 , wherein the memory access operation specified by the memory access command includes one of: a write operation, a read operation, or an erase operation.

4. The method of claim 1 , wherein performing the at least one memory access operation specified by the at least one memory access command includes performing the at least one memory access operation until a total execution time of the at least one memory access operation exceeds a maximum execution time.

5. The method of claim 4 , wherein the maximum execution time is based on an amount of time it takes to perform a flush operation on a predefined portion of the address mapping table.

6. The method of claim 1 , wherein the predefined portion of the address mapping table is a predetermined data size.

7. The method of claim 6 , wherein the predetermined data size is a size of a data unit.

8. The method of claim 7 , further comprising:
responsive to receiving a subsequent memory access command, suspending the flush operation after a second predefined portion of the address mapping table is flushed;
performing a subsequent memory access operations specified by the subsequent memory access command; and
resuming the performance of the flush operation on the address mapping table.

9. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
receiving a table flush command;
reading, from a volatile memory device, a predefined portion of an address mapping table;
writing, to a non-volatile memory device, the predefined portion of the address mapping table;
receiving at least one memory access command;
responsive to determining that the predefined portion is not the last portion of the address mapping table, performing at least one memory access operation specified by the at least one memory access command; and
determining whether a memory access command criterion is satisfied.

10. The non-transitory computer-readable storage medium of claim 9 , wherein determining whether the memory access command criterion is satisfied includes determining whether a total execution time of the at least one memory access operation exceeds a maximum execution time.

11. The non-transitory computer-readable storage medium of claim 10 , wherein the maximum execution time is based on an amount of time it takes to perform a flush operation on a predefined portion of the address mapping table.

12. The non-transitory computer-readable storage medium of claim 9 , wherein the predefined portion of the address mapping table is a predetermined data size.

13. A system comprising:
one or more memory devices; and
a processing device, coupled to the one or more memory devices, to perform operations comprising:
responsive to receiving a table flush command,
performing a flush operation on the address mapping table;
responsive to receiving at least one memory access command, suspending the flush operation after a predefined portion of the address mapping table is flushed;
performing at least one memory access operation specified by the at least one memory access command; and
resuming the performance of the flush operation on the address mapping table.

14. The system of claim 13 , wherein performing the flush operation includes reading the address mapping table from a volatile memory device and writing the address mapping table to a non-volatile memory device.

15. The system of claim 13 , wherein the memory access operation specified by the memory access command includes one of: a write operation, a read operation, or an erase operation.

16. The system of claim 13 , wherein performing the at least one memory access operation specified by the at least one memory access command includes performing the at least one memory access operation until a total execution time of the at least one memory access operation exceeds a maximum execution time.

17. The system of claim 16 , wherein the maximum execution time is based on an amount of time it takes to perform a flush operation on a predefined portion of the address mapping table.

18. The system of claim 13 , wherein the predefined portion of the address mapping table is a predetermined data size.

19. The system of claim 18 , wherein the predetermined data size is a size of a data unit.

20. The system of claim 13 , wherein the operations further comprise:
responsive to receiving a subsequent memory access command, suspending the flush operation after a second predefined portion of the address mapping table is flushed;
performing a subsequent memory access operations specified by the subsequent memory access command; and
resuming the performance of the flush operation on the address mapping table.

Assignees

• Micron Technology Inc

Inventors

• Chen Yuehhung
• Kao Chih-Kuo
• Zhu Fangfang
• Zhu Jiangli

Classifications

• G06F12/0292 Primary

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0652

  Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title