Automatic memory overclocking

Patent metadata

Field	Value
Publication number	US-11720266-B2
Application number	US-202217591924-A
Country	US
Kind code	B2
Filing date	Feb 3, 2022
Priority date	Dec 30, 2019
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

Automatic memory overclocking, including: increasing a memory frequency setting for a memory module until a memory stability test fails; determining an overclocked memory frequency setting including a highest memory frequency setting passing the memory stability test; and generating a profile including the overclocked memory frequency setting.

First claim

What is claimed is:

1. An apparatus for automatic memory overclocking, the apparatus comprising:
a computer processor; and
a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to:
increase a memory frequency setting for a memory module until a memory stability test fails; and
generate a profile comprising an overclocked memory frequency setting and one or more memory timing settings that correspond to the overclocked memory frequency setting, wherein the overclocked memory frequency setting is based on a highest frequency setting that does not fail the memory stability test.

2. The apparatus of claim 1 , further comprising computer program instructions that, when executed by the computer processor, cause the apparatus to:
determine the overclocked memory frequency setting, including:
modifying, for a particular memory frequency setting that failed the memory stability test, the one or more memory timing settings until the particular memory frequency setting passes the memory stability test; and
determining, as the overclocked memory frequency setting, the particular memory frequency setting.

3. The apparatus of claim 1 , wherein the one or more memory timing settings comprise one or more of: a Column Access Strobe (CAS) latency, a Row Address Strobe (RAS) to Column Address Strobe (CAS) Delay (Write), a Row Address Strobe (RAS) to Column Address Strobe (CAS) Delay (Read), a Row Precharge Time, and/or a Row Active Time.

4. The apparatus of claim 1 , wherein the computer program instructions further cause the apparatus to:
determine one or more subtiming settings based on the overclocked memory frequency setting and the one or more memory timing settings,
wherein generating the profile comprises including the one or more subtiming settings in the profile.

5. The apparatus of claim 4 , wherein the one or more subtiming settings are based on one or more rules applied to the overclocked memory frequency setting and/or the one or more memory timing settings.

6. The apparatus of claim 1 , wherein the computer program instructions further cause the apparatus to store the profile in a storage location.

7. The apparatus of claim 6 , wherein the computer program instructions further cause the apparatus to:
load the profile from the storage location; and
apply the profile to the memory module.

8. A method of automatic memory overclocking, the method comprising:
increasing a memory frequency setting for a memory module until a memory stability test fails; and
generating a profile comprising an overclocked memory frequency setting and one or more memory timing settings that correspond to the overclocked memory frequency setting, wherein the overclocked memory frequency setting is based on a highest frequency setting that does not fail the memory stability test.

9. The method of claim 8 , further comprising:
determining the overclocked memory frequency setting, including:
modifying, for a particular memory frequency setting that failed the memory stability test, the one or more memory timing settings until the particular memory frequency setting passes the memory stability test; and
determining, as the overclocked memory frequency setting, the particular memory frequency setting.

10. The method of claim 8 , wherein the one or more memory timing settings comprise one or more of: a Column Access Strobe (CAS) latency, a Row Address Strobe (RAS) to Column Address Strobe (CAS) Delay (Write), a Row Address Strobe (RAS) to Column Address Strobe (CAS) Delay (Read), a Row Precharge Time, and/or a Row Active Time.

11. The method of claim 8 , further comprising:
determining one or more subtiming settings based on the overclocked memory frequency setting and the one or more memory timing settings,
wherein generating the profile comprises including the one or more subtiming settings in the profile.

12. The method of claim 11 , wherein the one or more subtiming settings are based on one or more rules applied to the overclocked memory frequency setting and/or the one or more memory timing settings.

13. The method of claim 8 , further comprising storing the profile in a storage location.

14. The method of claim 13 , further comprising:
loading the profile from the storage location; and
applying the profile to the memory module.

15. A computer program product, comprising:
a non-transitory computer readable medium comprising computer program instructions that, when executed:
increase a memory frequency setting for a memory module until a memory stability test fails; and
generate a profile comprising an overclocked memory frequency setting and one or more memory timing settings that correspond to the overclocked memory frequency setting, wherein the overclocked memory frequency setting is based on a highest frequency setting that does not fail the memory stability test.

16. The computer program product of claim 15 , further comprising computer program instructions that, when executed:
determine the overclocked memory frequency setting, including:
modifying, for a particular memory frequency setting that failed the memory stability test, the one or more memory timing settings until the particular memory frequency setting passes the memory stability test; and
determining, as the overclocked memory frequency setting, the particular memory frequency setting.

17. The computer program product of claim 16 , wherein the one or more memory timing settings comprise one or more of: a Column Access Strobe (CAS) latency, a Row Address Strobe (RAS) to Column Address Strobe (CAS) Delay (Write), a Row Address Strobe (RAS) to Column Address Strobe (CAS) Delay (Read), a Row Precharge Time, and/or a Row Active Time.

Assignees

• Advanced Micro Devices Inc

Inventors

• Alverson William R
• Mehra Amitabh
• Harwani Anil
• Ahrens Jerry A
• Ley Grant E
• Joshi Jayesh

Classifications

• G06F3/0632 Primary

  by initialisation or re-initialisation of storage systems · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0673

  Single storage device · CPC title

• G11C29/10

  Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns · CPC title

• G11C29/50012 Primary

  of timing · CPC title