Guaranteed data compression using intermediate compressed data

Patent metadata

Field	Value
Publication number	US-11716094-B2
Application number	US-202217751583-A
Country	US
Kind code	B2
Filing date	May 23, 2022
Priority date	Jun 29, 2018
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

Methods for converting an n-bit number into an m-bit number for situations where n>m and also for situations where n<m, where n and m are integers. The methods use truncation or bit replication followed by the calculation of an adjustment value which is applied to the replicated number.

First claim

What is claimed is:

1. A method of converting, in hardware, an input number to an output m-bit number, the method comprising:
determining, in a truncation unit, an intermediate m-bit number; and
generating the output m-bit number by adding an adjustment value to the intermediate m-bit number.

2. The method according to claim 1 , further comprising setting the adjustment value, wherein setting the adjustment value comprises:
for each of a plurality of pre-determined subsets of the bits of the input number, using a plurality of AND logic blocks to compare the subset to a pre-defined bit sequence; and
in response to identifying a match between a subset and its corresponding pre-defined bit sequence, setting the adjustment value to a value associated with the pre-defined bit sequence.

3. The method of claim 1 , wherein the method is used in a method of frame buffer compression.

4. The method of claim 3 , wherein the method of frame buffer compression further comprises:
storing one or more bits of pixel data in a frame buffer; and
outputting the stored one or more bits of pixel data to a display.

5. Hardware logic configured to perform the method of claim 1 , optionally wherein the hardware logic is embodied in hardware on an integrated circuit.

6. A data compression unit comprising the hardware logic according to claim 5 .

7. A non-transitory computer readable storage medium having stored thereon computer executable code that when executed causes at least one processor to perform the method as set forth in claim 1 .

8. A method of converting, in hardware, an input number to an output m-bit number, the method comprising:
determining, in a replication unit, an intermediate m-bit number; and
generating the output m-bit number by adding an adjustment value to the intermediate m-bit number.

9. The method according to claim 8 , wherein n is a number of bits in the input number, and further wherein if m>2n, determining an intermediate m-bit number comprises:
appending (k−1) repetitions of the input number to the input number followed by r most significant bits of the input number, where k=└(m/n)┘ and r=m mod n.

10. The method according to claim 8 , further comprising setting the adjustment value, wherein setting the adjustment value comprises:
for each of a plurality of pre-determined subsets of the bits of the input number, using a plurality of AND logic blocks to compare the subset to a pre-defined bit sequence; and
in response to identifying a match between a subset and its corresponding pre-defined bit sequence, setting the adjustment value to a value associated with the pre-defined bit sequence.

11. Hardware logic configured to perform the method of claim 8 , optionally wherein the hardware logic is embodied in hardware on an integrated circuit.

12. A data compression unit comprising the hardware logic according to claim 11 .

13. A non-transitory computer readable storage medium having stored thereon computer executable code that when executed causes at least one processor to perform the method as set forth in claim 8 .

14. Hardware logic arranged to convert, in hardware, an input number to an output m-bit number, the hardware logic comprising:
a truncation unit arranged to determine an intermediate m-bit number; and
an addition unit arranged to add an adjustment value to the intermediate m-bit number to generate the output m-bit number.

15. A data compression unit comprising the hardware logic according to claim 14 .

16. A method of manufacturing hardware logic as set forth in claim 14 , comprising using an integrated circuit manufacturing system.

17. An integrated circuit definition dataset embodied in a non-transitory storage medium that, when processed in an integrated circuit manufacturing system, configures the integrated circuit manufacturing system to manufacture hardware logic as set forth in claim 14 .

18. A non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture hardware logic as set forth in claim 14 .

19. An integrated circuit manufacturing system configured to manufacture hardware logic as set forth in claim 14 .

20. An integrated circuit manufacturing system comprising:
a non-transitory computer readable storage medium having stored thereon a computer readable dataset description of an integrated circuit that describes hardware logic as set forth in claim 14 ;
a layout processing system configured to process the integrated circuit description so as to generate a circuit layout description of an integrated circuit embodying the hardware logic; and
an integrated circuit generation system configured to manufacture the hardware logic according to the circuit layout description.

Assignees

• Imagination Tech Ltd

Inventors

• Fenney Simon

Classifications

• H03M7/30 Primary

  Compression (speech analysis-synthesis for redundancy reduction G10L19/00; for image communication H04N); Expansion; Suppression of unnecessary data, e.g. redundancy reduction · CPC title

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06T1/60

  Memory management · CPC title

• G06T9/00

  Image coding (bandwidth or redundancy reduction for static pictures H04N1/41; coding or decoding of static colour picture signals H04N1/64; methods or arrangements for coding, decoding, compressing or decompressing digital video signals H04N19/00) · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title