Semiconductor device and method of inspecting the same

Patent metadata

Field	Value
Publication number	US-11715701-B2
Application number	US-201916386774-A
Country	US
Kind code	B2
Filing date	Apr 17, 2019
Priority date	Sep 10, 2013
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

According to one embodiment, a semiconductor device includes a wiring board that has a first surface and a second surface opposed to the first surface, a semiconductor chip provided on the first surface, external connection terminals provided on the second surface, a sealing resin layer provided on the first surface, and a conductive shield layer that covers at least a portion of a side surface of the wiring board and the sealing resin layer. The wiring board includes a first ground wire that is electrically connected to the conductive shield layer, and a second ground wire that is electrically connected to the conductive shield layer and is electrically insulated from the first ground wire.

First claim

What is claimed is:

1. A method of inspecting a semiconductor device, the method comprising:
measuring a resistance value between a first terminal and second terminal;
determining a connection state of a first wire and a second wire to a conductive shield layer based on the resistance value, wherein the semiconductor device comprises:
a wiring board having a first surface, a second surface, the first wire, and the second wire, the first terminal being on the second surface and the second terminal being on the second surface;
a semiconductor chip on the first surface;
a sealing resin layer on the first surface and sealing the semiconductor chip; and
the conductive shield layer covering at least a portion of side surfaces of the wiring board and the sealing resin layer, wherein
the first wire and the second wire are electrically insulated from each other on the wiring board,
the conductive shield layer is electrically connected to the first wire and the second wire at different edges of the first surface of the wiring board,
the first wire includes a first extending portion on the first surface of the wiring board,
the second wire includes a second extending portion on the first surface of the wiring board,
the first extending portion directly contacts the conductive shield at a first edge of the wiring board,
the second extending portion directly contacts the conductive shield at a second edge of the wiring board, and
the resistance value includes a first contact resistance between the first extending portion and the conductive shield layer and a second contact resistance between the second extending portion and the conductive shield layer.

2. The method according to claim 1 , wherein
the first terminal is an external connection terminal, and
the second terminal is an inspection terminal.

3. The method according to claim 1 , wherein the semiconductor chip is mounted above a portion of the first wire and a portion of the second wire.

4. The method according to claim 1 , wherein
the second edge is opposite from the first edge, and
the conductive shield extends at least partially past the first surface of the wiring board toward the second surface of the wiring board.

5. The method according to claim 1 , wherein
the first and second extending portion each extend to past the edges of the first surface of the wiring board on a side surface of the wiring board, and
the conductive shield extends at least partially over the side surface of the wiring board.

6. The method according to claim 1 , wherein
the ends of the first and second extending portions are exposed at an outer edge of the first surface of the wiring board, and
the conductive shield connects to the first and second wires only at the outer edge of the first surface of the wiring board.

7. The method according to claim 1 , wherein the wiring board includes a solid film overlapping the location of the semiconductor chip on the wiring board.

8. The method according to claim 1 , wherein the wiring board includes a mesh film overlapping the location of the semiconductor chip on the wiring board.

9. A method of inspecting a semiconductor device, comprising:
electrically connecting a first grounding wire that is between a first surface of a wiring board and a second surface of the wiring board to a first ground terminal on the second surface through a first via;
electrically connecting a second grounding wire that is between the first surface and the second surface to a second ground terminal on the second surface through a second via;
electrically connecting a conductive shield layer to the first grounding wire through the first via;
electrically connecting the conductive shield layer to the second grounding wire through the second via;
measuring a resistance value between the first ground terminal and the second ground terminal of the semiconductor device; and
determining the connection state of the first grounding wire and the second grounding wire to the conductive shield layer based on the measured resistance value, wherein
the first and second grounding wires are electrically isolated from one another on the wiring board and electrically connected to the conductive shield layer at different side surfaces of the wiring board,
the first via electrically connects to the conductive shield layer through a first extending portion provided on the first surface at a first edge of the wiring board, and
the second via electrically connects to the conductive shield layer through a second extending portion provided on the first surface at a second edge of the wiring board,
the first extending portion directly contacts the conductive shield at the first edge of the wiring board,
the second extending portion directly contacts the conductive shield at the second edge of the wiring board, and
the resistance value includes a first contact resistance between the first extending portion and the conductive shield layer and a second contact resistance between the second extending portion and the conductive shield layer.

10. The method of claim 9 , wherein
the first and second edges of the wiring board are opposite outer edges of the wiring board, and
the first and second extending portions extend on at least a portion of the outer edges of the wiring board.

11. The method of claim 9 , wherein a semiconductor chip is mounted to the first surface of the wiring board.

12. The method of claim 11 , wherein the semiconductor chip covers a portion of the first grounding wire and a portion of the second grounding wire.

13. The method according to claim 11 , wherein the wiring board includes a solid film overlapping the location of the semiconductor chip on the wiring board.

14. The method according to claim 11 , wherein the wiring board includes a mesh film overlapping the location of the semiconductor chip on the wiring board.

15. The method of according to claim 1 , wherein measuring the resistance value does not include physically contacting the conductive shield layer with a tester.

16. The method according to claim 9 , wherein
the first extending portion divides into a plurality of separate portions on the first surface each of the separate portions of the first extending portion directly contacts the conductive shield layer at a different location spaced from each other location along the first edge, and
the second extending portion divides into a plurality of separate portions on the first surface each of the separate portions of the second extending portion directly contacts the conductive shield layer at a different location spaced from each other location along the second edge.

17. The method of according to claim 9 , wherein measuring the resistance does not include physically contacting the conductive shield layer with a tester.

Assignees

• Toshiba Memory Corp
• Kioxia Corp

Inventors

• Takano Yuusuke
• Goto Yoshiaki
• Watanabe Takeshi
• Imoto Takashi

Classifications

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W72/50

  Bond wires · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title