Display panel, display device and driving method

Patent metadata

Field	Value
Publication number	US-11715401-B2
Application number	US-201916957575-A
Country	US
Kind code	B2
Filing date	Jul 31, 2019
Priority date	Jul 31, 2019
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

A display panel, a display device and a driving method. The display panel includes a display region and a peripheral region. The display region includes a subpixel unit array having a plurality of rows and a plurality of columns of subpixel units, and the peripheral region includes a gate drive circuit. The display region further includes a plurality of gate lines and a plurality of data lines. Each subpixel unit is driven by a scanning signal provided by one gate and a data signal provided by one data line, and a same data line is connected with at least two subpixel units which are not adjacent to each other and have a same color. The gate drive circuit includes a plurality of shift register units, and the plurality of gate lines are electrically connected with the plurality of shift register units in a one-to-one correspondence in order.

First claim

What is claimed is:

1. A display panel, comprising a display region and a peripheral region,
wherein the display region comprises a subpixel unit array having a plurality of rows and a plurality of columns of subpixel units, and the peripheral region comprises a gate drive circuit;
the display region further comprises a plurality of gate lines and a plurality of data lines for driving the subpixel unit array, each subpixel unit is driven by a scanning signal provided by one gate line of the plurality of gate lines and a data signal provided by one data line of the plurality of data lines to display, and a same data line is connected with at least two subpixel units which are not adjacent to each other and have a same color;
the gate drive circuit comprises a plurality of shift register units arranged in sequence, and the plurality of gate lines are arranged in sequence and electrically connected with the plurality of shift register units arranged in sequence in a one-to-one correspondence in order; and
the gate drive circuit is configured to receive clock signals and generate the scanning signal to enable the at least two subpixel units of the same color which are connected with the same data line and not adjacent to each other to display successively in timing
wherein the plurality of shift register units are divided into at least one shift-register-unit scanning group,
each of the at least one shift-register-unit scanning group comprises a plurality of shift register unit groups formed by adjacent and cascaded shift register units, and
every two adjacent shift register unit groups are not cascaded.

2. The display panel according to claim 1 , wherein
a plurality of subpixel units connected with the same data line in sequence are divided into G driving groups when driven, a number of the clock signals is H, each of the driving groups comprises F subpixel units, F=[H/G], and [H/G] denotes rounding H/G; and
the gate drive circuit is further configured to enable F subpixel units in a Bth driving group to be driven in an order of A d =B+(d−1)×G, A d denotes an order number of the subpixel unit which is driven for a dth time, B is a positive integer less than or equal to G, and d is a positive integer less than or equal to F.

3. The display panel according to claim 2 , wherein the plurality of subpixel units connected with the same data line in sequence have at least a first color and a second color; and
among the plurality of subpixel units connected with the same data line in sequence, the subpixel units of the first color have a minimum arrangement period of G1, the subpixel units of the second color have a minimum arrangement period of G2, and then G is a least common multiple of G1 and G2.

4. The display panel according to claim 1 , wherein each of the at least one shift-register-unit scanning group comprises 16 shift register units, and in each of the at least one shift-register-unit scanning group, (k+1)th and kth shift register units are cascaded to form one shift register unit group, (k+1)th and (k+2)th shift register units are not cascaded, and k is 1, 3, 5, 7, 9, 11, 13 or 15.

5. The display panel according to claim 4 , wherein the gate drive circuit comprises a plurality of shift-register-unit scanning groups, and a kth shift register unit in one of two adjacent shift-register-unit scanning groups is connected with a (k+1)th shift register unit in a remaining one of the two adjacent shift-register-unit scanning groups, and k is 1, 3, 5, 7, 9, 11, 13 or 15.

6. The display panel according to claim 4 , wherein the clock signals received by the 16 shift register units in each of the at least one shift-register-unit scanning group are a first clock signal to a sixteenth clock signal, and the first clock signal to the sixteenth clock signal have equal periods and equal duty ratios.

7. The display panel according to claim 6 , wherein the period comprises 16 time units, and the first, fifth, ninth, thirteenth, third, seventh, eleventh and fifteenth clock signals are adjacent to each other in sequence in timing;
the second, sixth, tenth, fourteenth, fourth, eighth, twelfth and sixteenth clock signals are adjacent to each other in sequence in timing; and
the first and second clock signals differ in timing by 8 time units.

8. The display panel according to claim 6 , wherein the duty ratio is 9/20.

9. The display panel according to claim 2 , wherein the subpixel unit array is divided into at least one subpixel-unit scanning group in a one-to-one correspondence with the at least one shift-register-unit scanning group.

10. The display panel according to claim 9 , wherein each of the at least one shift-register-unit scanning group comprises 16 shift register units;
each of the at least one subpixel-unit scanning group comprises 8 adjacent rows of subpixel units; and
a qth row of subpixel units in each of the at least one subpixel-unit scanning group is electrically connected with a (2q−1)th shift register unit and a (2q)th shift register unit in the shift- register-unit scanning group corresponding to the subpixel-unit scanning group, and q is an integer greater than or equal to 1 and less than or equal to 8.

11. The display panel according to claim 10 , wherein one gate line is provided at each of two sides of each row of subpixel units, and each row of subpixel units is connected with two gate lines respectively provided at the two sides of each row of subpixel units.

12. The display panel according to claim 1 , wherein
the display panel further comprises a data drive circuit in the peripheral region, and the data drive circuit is connected with the plurality of data lines and configured to supply the data signal to the subpixel unit array by means of a 2-point polarity switching approach.

13. The display panel according to claim 12 , wherein
the data signal provided by any one of the plurality of data lines has a same polarity, and
the any one of the plurality of data lines has a zigzag wiring shape.

14. The display panel according to claim 1 , wherein in each of the at least one shift-register-unit scanning group, a Lth shift register unit is provided at a first side of the display region, a Rth shift register unit is provided at a second side of the display region opposite to the first side; and
L is 1, 2, 3, 4, 9, 10, 11 or 12, and R is 5, 6, 7, 8, 13, 14, 15 or 16.

15. A display device, comprising a display panel,
wherein display panel comprises a display region and a peripheral region,
the display region comprises a subpixel unit array having a plurality of rows and a plurality of columns of subpixel units, and the peripheral region comprises a gate drive circuit;
the display region further comprises a plurality of gate lines and a plurality of data lines for driving the subpixel unit array, each subpixel unit is driven by a scanning signal provided by one gate line of the plurality of gate lines and a data signal provided by one data line of the plurality of data lines to display, and a same data line is connected with at least two subpixel units which are not adjacent to each other and have a same color;
the gate drive circuit comprises a plurality of shift register units arranged in sequence, and the plurality of gate lines are arranged in sequence and electrically connected with the plurality of shift register units arranged in sequence in a one-to-one correspondence in order; and
the gate drive circuit is configured to receive clock signals and generate the scanning signal to enable the at least two subpixel units of the same color which are connected with the same data line and not adja

Assignees

• Beijing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Meng Zhaohui
• Sun Wei
• Han Wenchao
• Yang Hong
• Cong Lin
• Xiao Wenjun

Classifications

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2310/0254

  Control of polarity reversal in general, other than for liquid crystal displays · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/0275

  Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title