Systems and methods of power management

Patent metadata

Field	Value
Publication number	US-11714564-B2
Application number	US-202016735606-A
Country	US
Kind code	B2
Filing date	Jan 6, 2020
Priority date	Jan 6, 2020
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

According to one implementation of the present disclosure, a method for power management is disclosed. The method includes: computing, by a central processing unit, software instructions of a software workload in an active-mode operation corresponding to a first operating point on a performance curve of a performance mode; transitioning from instances of the active-mode operation to instances of standby-mode operation of the CPU, and recording, by a time tracking element, each of a plurality of standby entry data points; transitioning from the instances of the standby-mode operation to the instances of the active-mode operation of the CPU, and recording, by the time tracking element, each of a plurality of standby exit data points; and determining a second operating point on the performance curve of the performance mode based on the recorded standby entry data points and the recorded standby exit data points.

First claim

What is claimed is:

1. A method of power management comprising:
computing, by a central processing unit (CPU), software instructions of a software workload in an active-mode operation corresponding to a first operating point on a performance curve of a performance mode;
transitioning from instances of the active-mode operation to instances of standby-mode operation of the CPU;
transitioning from the instances of the standby-mode operation to the instances of the active-mode operation of the CPU; and
determining a second operating point on the performance curve of the performance mode based on a first and second of a plurality of standby entry data points and a first and second of a plurality of standby exit data points, wherein:
the first standby exit data point is sequential with the first standby entry data point,
the second standby exit point is sequential with the second entry data point,
the plurality of standby entry data points corresponds to the transitions from the active mode operation to the standby-mode operation,
the plurality of standby exit data points corresponds to the transitions from the standby-mode operation to the active-mode operation, and
the difference between the first standby exit data point and the first standby entry data point is different from the difference between the second standby exit data point and the second standby entry data point.

2. The method of claim 1 , further comprising:
enacting the performance mode based on the second operating point, wherein enacting the performance mode comprises providing, by a power management unit (PMU), an operating voltage and a clock signal to the CPU, and wherein the performance mode corresponds to either a dynamic voltage frequency scaling (DVFS) mode or a body-biasing for frequency scaling at ISO-voltage mode.

3. The method of claim 1 , wherein the transitions to the standby-mode operation are performed in response to one of: a sleep-mode of the CPU or a wait-for-interrupt (WFI) instruction, and wherein the transitions to the active-mode operation are performed in response to one of: active-mode operation requests of the CPU, activations of an alarm of the time tracking element, internal interrupt instructions, or external interrupt instructions.

4. The method of claim 1 , further comprising:
recording at least a portion of the plurality of the standby entry data points and recording at least a portion of the plurality of the standby exit data points into a programmable memory of the CPU or the PMU.

5. The method of claim 1 , wherein determining the second operating point comprises one or more of:
evaluating at least a portion of the plurality of the standby entry data points and at least a portion of the plurality of the standby exit data points;
determining a cost of changing the first operating point;
determining a power supply latency,
determining time intervals of the software workload, and
determining time intervals of transitions from the active-mode operation to the standby-mode operation and the standby-mode operation to the active-mode operation.

6. The method of claim 5 , wherein evaluating at least the portion of the plurality of the standby entry data points and at least the portion of the plurality of the standby exit data points comprise:
computing a duty cycle and a minimum time interval for the standby-mode operation, wherein the duty cycle corresponds to a quotient of a weighted active time interval and a weighted standby time interval of the software workload.

7. The method of 1 , wherein the second operating point corresponds to a decrease from the first operating point on the performance mode curve of a performance operating map, and wherein the decrease corresponds to a shortening of the active phase operation.

8. The method of claim 1 , wherein the software workload comprises either a single-phase or a multi-phase workload.

9. The method of claim 8 , wherein if the software workload comprises the multi-phase workload, the second operating point corresponds to a second DVFS mode that is configured to set the active-mode operation as substantially equal to an active mode of a code phase having a longest time interval.

10. The method of claim 8 , wherein if the software workload comprises the multi-phase workload, further comprising:
classifying one or more code phases of the multi-phase workload, wherein each code phase of the one or more code phases corresponds to a particular software workload of the multi-phase workload;
tracking one or more code phases by recording the standby entry data points and the standby exit data points corresponding to respective classified software workloads; and
determining different operating points on respective performance curves for each of the tracked code phases.

11. The method of claim 1 , wherein a time tracking element is configured to track the transitions from the active-mode operation to the standby-mode operation, and the transitions from the standby-mode operation to the active-mode operation, and wherein the time tracking element comprises one of a real-time clock (RTC), voltage measurement device, resistor-capacitor (RC) time-constants, and a leakage measurement.

12. A system comprising:
a central processing unit (CPU);
a power management unit (PMU) coupled to the CPU; and
a time tracking element coupled to the CPU and the PMU, wherein:
the PMU is configured to control the time tracking element to record sequential standby entry and exit data points of one or more code phases of a software workload, and
the CPU is configured to determine an operating point on a performance curve based on a first and second of the standby data entry points and a first and second of the standby exit data points, wherein:
the first standby exit data point is sequential with the first standby entry data point,
the second standby exit point is sequential with the second entry data point,
the standby entry data points corresponds to the transitions from an active-mode operation to a standby-mode operation,
the standby exit data points corresponds to the transitions from the standby mode operation to the active-mode operation, and
the difference between the first standby exit data point and the first standby entry data point is different from the difference between second standby exit data point and the second standby entry data point.

13. The system of claim 12 , wherein the PMU is configured to: sequence the CPU into instances of standby mode operation upon notification that the CPU is in a low power state, initiate active-mode operation of the CPU when the time tracking element is activated, and initialize software instructions of the software workload.

14. The system of claim 12 , wherein the CPU is configured to evaluate the recorded standby entry and exit data points based on standby periodicity and standby regularity.

15. The system of claim 12 , wherein an alarm triggered by the time tracking element is configured to provide subsequent initiations of active mode operation of the CPU.

16. The system of claim 12 , wherein the PMU is configured to provide an operating voltage and a clock signal to enact a second operating point.

17. The system of claim 12 , wherein the performance curve corresponds to a dynamic voltage frequency scaling (DVFS) curve or a body-biasing for frequency scaling at ISO-voltage curve.

18. A method comprising:
sampling, by a microcontroller device of a power management unit (PMU), sequential standby time values of a software workload upon power-mode changes, wherein th

Assignees

• Advanced Risc Mach Ltd

Inventors

• Myers James Edward
• Prabhat Pranay
• Walker Matthew James
• Savanth Parameshwarappa Anand Kumar
• Redondo Fernando Garcia

Classifications

• G06F3/0634 Primary

  by changing the state or mode of one or more devices · CPC title

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title

• G06F3/0625

  Power saving in storage systems · CPC title