Array substrate and manufacturing method thereof and touch display panel

Patent metadata

Field	Value
Publication number	US-11714513-B2
Application number	US-202117427072-A
Country	US
Kind code	B2
Filing date	Jan 6, 2021
Priority date	Jan 21, 2020
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

An array substrate includes: a plurality of touch units arranged in an array and insulated from each other; each of the plurality of touch units including at least one electrode block arranged in an array and connected to each other; and a plurality of touch lines; wherein the touch units and the touch lines are connected in a one-to-one correspondence by direct overlap. Also disclosed are a touch display panel and a method for manufacturing the array substrate.

First claim

What is claimed is:

1. An array substrate comprising:
a plurality of touch units arranged in an array and insulated from each other, each of the plurality of touch units comprising at least one electrode block arranged in an array and connected to each other;
a plurality of touch lines; and
a plurality of data lines,
wherein the touch units and the touch lines are connected in a one-to-one correspondence with each other by direct contact;
wherein the electrode blocks and the touch lines contact directly without an intermediate layer therebetween,
wherein a pair of the touch lines is provided on both sides of a corresponding one of the data lines and the pair of the touch lines are insulated from each other;
wherein the touch lines are opaque;
wherein any two of the touch lines are insulated from each other.

2. The array substrate according to claim 1 , wherein all the electrode blocks of the plurality of touch units receive a common voltage from the plurality of touch lines for display within a first time, and receive a touch voltage from the plurality of touch lines within a second time, to detect a change in capacitance of the plurality of touch lines, and determine a touch position.

3. The array substrate according to claim 2 , further comprising:
a base substrate;
a thin film transistor disposed on the base substrate;
a passivation protection layer disposed on the thin film transistor;
a pixel electrode disposed on the passivation protection layer; and
an insulating protection layer disposed on the pixel electrode;
wherein the at least one electrode block of the plurality of touch units is disposed on the insulating protection layer.

4. The array substrate according to claim 1 , further comprising:
a base substrate;
a thin film transistor disposed on the base substrate;
a passivation protection layer disposed on the thin film transistor;
a pixel electrode disposed on the passivation protection layer; and
an insulating protection layer disposed on the pixel electrode;
wherein the at least one electrode block of the plurality of touch units is disposed on the insulating protection layer.

5. The array substrate according to claim 4 , wherein the thin film transistor comprises:
a gate electrode disposed on the base substrate;
a gate insulating layer disposed on the gate electrode;
an active layer disposed on the gate insulating layer; and
a source electrode and a drain electrode, disposed on the active layer.

6. The array substrate according to claim 5 , wherein the data lines are in the same layer as the source electrode and the drain electrode.

7. The array substrate according to claim 6 , wherein the electrode blocks comprise slits arranged side by side, and extending directions of the slits are parallel to an extending direction of the data lines.

8. The array substrate according to claim 7 , wherein one of the touch units comprises at least two electrode blocks, and the array substrate further comprises a connecting line in the same layer as the gate electrode, and the at least two electrode blocks are respectively connected to the connecting line through a via hole.

9. The array substrate according to claim 6 , wherein one of the touch units comprises at least two electrode blocks, and the array substrate further comprises a connecting line in the same layer as the gate electrode, and the at least two electrode blocks are respectively connected to the connecting line through a via hole.

10. The array substrate according to claim 4 , wherein the insulating protection layer has a thickness of 0.8 to 2.5 microns.

11. A touch display panel comprising the array substrate according to claim 1 , a counter substrate and a liquid crystal layer, the liquid crystal layer being disposed between the array substrate and the counter substrate.

12. A method for manufacturing the array substrate according to claim 1 , comprising:
forming a first transparent conductive layer, a metal layer, and a first photoresist layer, wherein the metal layer is disposed on the first transparent conductive layer, and the first photoresist layer is disposed on the metal layer;
placing a first halftone mask on the first photoresist layer, and exposing and developing the first photoresist layer to obtain a second photoresist layer comprising a hollowed portion, a first blocking portion and a second blocking portion, the first blocking portion having a thickness larger than a thickness of the second blocking portion;
etching the metal layer disposed under the hollowed portion to expose the first transparent conductive layer under the hollowed portion;
etching the first transparent conductive layer under the hollowed portion to obtain electrode blocks arranged in an array;
ashing the first blocking portion and the second blocking portion, and removing the second blocking portion, wherein the first blocking portion is ashed to obtain a third blocking portion; and
etching the metal layer that is not covered by the third blocking portion to obtain touch lines,
wherein the array substrate comprises a plurality of data lines,
wherein the touch units and the touch lines are connected in a one-to-one correspondence with each other by direct contact;
wherein the electrode blocks and the touch lines contact directly without an intermediate layer therebetween,
wherein a pair of the touch lines is provided on both sides of a corresponding one of the data lines, and the pair of the touch lines are insulated from each other;
wherein the touch lines are opaque;
wherein any two of the touch lines are insulated from each other.

13. The array substrate according to claim 1 , wherein the electrode blocks comprise slits arranged side by side, and extending directions of the slits are parallel to an extending direction of the data lines.

14. The array substrate according to claim 1 , wherein one of the touch units comprises at least two electrode blocks, and the array substrate further comprises a connecting line in the same layer as the gate electrode, and the at least two electrode blocks are respectively connected to the connecting line through a via hole.

Assignees

• Wuhan Boe Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wang Chao
• Zhu Ning
• Gao Yujie

Classifications

• G06F3/0446 Primary

  using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G06F3/0412 Primary

  Digitisers structurally integrated in a display · CPC title

• G06F3/0443 Primary

  using a single layer of sensing electrodes · CPC title