Method and apparatus for testing artificial intelligence chip, device and storage medium

Patent metadata

Field	Value
Publication number	US-11714128-B2
Application number	US-202017021080-A
Country	US
Kind code	B2
Filing date	Sep 15, 2020
Priority date	Dec 31, 2019
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

The present disclosure discloses a method and an apparatus for testing an artificial intelligence chip test, a device and a storage medium, and relates to the field of artificial intelligence. The specific implementation solution is: the target artificial intelligence chip has multiple same arithmetic units, the method includes: obtaining scale information of the target artificial intelligence chip; determining whether the target artificial intelligence chip satisfies a test condition of an arithmetic unit array level according to the scale information; dividing all the arithmetic units into multiple same arithmetic unit arrays, and performing a DFT test on the arithmetic unit arrays, respectively, if it is determined that the test condition of the arithmetic unit array level is satisfied; performing the DFT test on the arithmetic units, respectively, if it is not determined that the test condition of the arithmetic unit array level is not satisfied.

First claim

What is claimed is:

1. A method for testing an artificial intelligence chip, wherein a target artificial intelligence chip has multiple same arithmetic units, and the method comprises:
obtaining scale information of the target artificial intelligence chip;
determining whether the target artificial intelligence chip satisfies a test condition of an arithmetic unit array level according to the scale information;
dividing all the arithmetic units into multiple same arithmetic unit arrays, and performing a Design for Test (DFT) test on the arithmetic unit arrays, respectively, upon determining that the test condition of the arithmetic unit array level is satisfied, wherein the performing the DFT test on the arithmetic unit arrays comprises performing, at the arithmetic unit array level, the DFT test on each of the arithmetic unit arrays;
performing the DFT test on the arithmetic units, respectively, upon determining that the test condition of the arithmetic unit array level is not satisfied, wherein the performing the DFT test on the arithmetic units comprises performing, at an arithmetic unit level, the DFT test on each of the arithmetic units;
wherein the scale information comprises a number of transistors in an arithmetic unit, and the determining whether the target artificial intelligence chip satisfies a test condition of an arithmetic unit array level according to the scale information, comprises:
determining whether the number of the transistors is smaller than a preset scale threshold;
determining that the test condition of the arithmetic unit array level is satisfied, upon determining that the number of the transistors is less than the preset scale threshold;
determining that the test condition of the arithmetic unit array level is not satisfied, upon determining that the number of the transistors is greater than or equal to the preset scale threshold.

2. The method according to claim 1 , wherein the dividing all the arithmetic units into multiple same arithmetic unit arrays, comprises:
determining a number of arithmetic units in an arithmetic unit array according to the number of the transistors and a total number of the arithmetic units;
dividing all the arithmetic units into the multiple same arithmetic unit arrays, according to the number of the arithmetic units.

3. The method according to claim 1 , wherein each of the arithmetic unit arrays is provided with a first test logic circuit;
the performing a DFT test on the arithmetic unit arrays, respectively, comprises:
generating first test vectors corresponding to the arithmetic unit arrays, wherein the first test vectors corresponding to respective ones of the arithmetic unit arrays are the same;
performing the DFT test on the arithmetic unit arrays, respectively, by inputting the first test vectors into first test logic circuits corresponding to respective ones of the arithmetic unit arrays, respectively;
outputting test results corresponding to respective ones of the arithmetic unit arrays.

4. The method according to claim 3 , wherein the first test logic circuit comprises: a first test interface;
the performing the DFT test on the arithmetic unit arrays, respectively, by inputting the first test vectors into first test logic circuits corresponding to respective ones of the arithmetic unit arrays, respectively, comprises:
performing the DFT test on the arithmetic unit arrays in parallel by broadcasting, through respective first test interfaces, the first test vectors to the first test logic circuits of corresponding arithmetic unit arrays.

5. The method according to claim 1 , wherein each of the arithmetic units is provided with a second test logic circuit;
the performing the DFT test on the arithmetic units, respectively, comprises:
generating second test vectors corresponding to the arithmetic units, wherein the second test vectors corresponding to respective ones of the arithmetic units are the same;
performing the DFT test on the arithmetic units, respectively, by inputting the second test vectors into second test logic circuits corresponding to respective ones of the arithmetic units, respectively;
outputting test results corresponding to respective ones of the arithmetic units.

6. The method according to claim 5 , wherein the second test logic circuit comprises: a second test interface;
the performing the DFT test on the arithmetic units, respectively, by inputting the second test vectors into second test logic circuits corresponding to respective ones of the arithmetic units, respectively, comprises:
performing the DFT test on the arithmetic units in parallel by broadcasting, through respective second test interfaces, the second test vectors to the second test logic circuits of corresponding arithmetic units.

7. The method according to claim 3 , wherein before the performing the DFT test on the arithmetic unit arrays, respectively, the method further comprises:
performing a test on at least one first preset DFT logic circuit in the first test logic circuit at a register-transfer level (RTL) stage of the target artificial intelligence chip;
repairing the first preset DFT logic circuit at the RTL stage of the target artificial intelligence chip, when the first preset DFT logic circuit fails the test.

8. The method according to claim 5 , wherein before the performing the DFT test on the arithmetic units, respectively, the method further comprises:
performing a test on at least one second preset DFT logic circuit in the second test logic circuit at an RTL stage of the target artificial intelligence chip;
repairing the second preset DFT logic circuit at the RTL stage of the target artificial intelligence chip, when the second preset DFT logic circuit fails the test.

9. An electronic device, comprising:
at least one processor; and
a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the at least one processor when executing the instructions is configured to:
obtain scale information of a target artificial intelligence chip;
determine whether the target artificial intelligence chip satisfies a test condition of an arithmetic unit array level according to the scale information;
divide all the arithmetic units into multiple same arithmetic unit arrays, and perform a Design for Test (DFT) test on the arithmetic unit arrays, respectively, upon determining that the test condition of the arithmetic unit array level is satisfied, wherein the performing the DFT test on the arithmetic unit arrays comprises performing, at the arithmetic unit array level, the DFT test on each of the arithmetic unit arrays;
perform the DFT test on the arithmetic units, respectively, upon determining that the test condition of the arithmetic unit array level is not satisfied, wherein the performing the DFT test on the arithmetic units comprises performing, at an arithmetic unit level, the DFT test on each of the arithmetic units;
wherein the scale information comprises a number of transistors in an arithmetic unit, and the at least one processor is further configured to:
determine whether the number of the transistors is smaller than a preset scale threshold;
determine the test condition of the arithmetic unit array level is satisfied, upon determining that the number of the transistors is less than the preset scale threshold;
determine the test condition of the arithmetic unit array level is not satisfied, upon determining that the number of the transistors is greater than or equal to the preset scale threshold.

10. The electronic device according to claim 9 , wherein when dividing all the arithmetic units into multiple same arithmetic unit a

Assignees

• Kunlunxin Tech Beijing Company Limited

Inventors

• Guo Ziyu

Classifications

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title

• G06N5/02

  Knowledge representation; Symbolic representation · CPC title

• G01R31/3193

  with comparison between actual response and known fault free response {(receiver details G01R31/31924)} · CPC title

• G01R31/31701

  Arrangements for setting the Unit Under Test [UUT] in a test mode · CPC title

• G01R31/31703

  Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193) · CPC title