Superconductor-semiconductor fabrication

Patent metadata

Field	Value
Publication number	US-11711986-B2
Application number	US-201716627703-A
Country	US
Kind code	B2
Filing date	Nov 30, 2017
Priority date	Jun 30, 2017
Publication date	Jul 25, 2023
Grant date	Jul 25, 2023

Abstract

A mixed semiconductor-superconductor platform is fabricated in phases. In a masking phase, a dielectric mask is formed on a substrate, such that the dielectric mask leaves one or more regions of the substrate exposed. In a selective area growth phase, a semiconductor material is selectively grown on the substrate in the one or more exposed regions. In a superconductor growth phase, a layer of superconducting material is formed, at least part of which is in direct contact with the selectively grown semiconductor material. The mixed semiconductor-superconductor platform comprises the selectively grown semiconductor material and the superconducting material in direct contact with the selectively grown semiconductor material.

First claim

The invention claimed is:

1. A method of fabricating a mixed semiconductor-superconductor platform, the method comprising:
in a masking phase, forming a dielectric mask on a substrate, such that the dielectric mask leaves two or more strips of the substrate exposed;
in a selective area growth phase, selectively growing a semiconductor material on the substrate in the two or more exposed strips of the substrate to form a network of in-plane nanowires; and
in a superconductor growth phase, forming a layer of superconducting material, at least part of which is in direct contact with the selectively grown semiconductor material in the two or more exposed strips of the substrate;
wherein the mixed semiconductor-superconductor platform comprises the selectively grown semiconductor material and the superconducting material in direct contact with the selectively grown semiconductor material.

2. The method of claim 1 , wherein the layer of superconducting material is epitaxially grown in the superconductor growth phase.

3. The method of claim 2 , wherein the superconducting material is epitaxially grown using molecular beam epitaxy (MBE).

4. The method of claim 3 , wherein the layer of superconducting material is formed, in the superconductor growth phase, using a beam.

5. The method of claim 4 , wherein the beam has a non-zero angle of incidence relative to the normal of a plane of the substrate.

6. The method of claim 1 , wherein the selective area growth phase and the superconductor growth phase are performed in a vacuum chamber, with the substrate remaining in the vacuum chamber and vacuum maintained throughout and in between those phases.

7. A method of fabricating a mixed semiconductor-superconductor platform, the method comprising:
in a masking phase, forming a dielectric mask on a substrate, such that the dielectric mask leaves one or more regions of the substrate exposed;
in a selective area growth phase, selectively growing a semiconductor material on the substrate in the one or more exposed regions; and
in a superconductor growth phase, forming a layer of superconducting material, at least part of which is in direct contact with the selectively grown semiconductor material;
wherein the mixed semiconductor-superconductor platform comprises the selectively grown semiconductor material and the superconducting material in direct contact with the selectively grown semiconductor material, and
wherein the layer of superconducting material is epitaxially grown in the superconductor growth phase using molecular beam epitaxy (MBE) with a beam having a non-zero angle of incidence relative to the normal of a plane of the substrate such that the beam is angled relative to the substrate, such that the beam is incident on one side of a structure protruding outwardly of the plane of the substrate, thereby preventing a shadow region on the other side of the protruding structure from being covered with the superconductor material.

8. The method of claim 7 , wherein the protruding structure is a protruding portion of the semiconductor material, such that the shadow region separates the semiconductor material from a portion of the superconductor material deposited in a gating region.

9. The method of claim 8 , comprising:
removing semiconductor material from the gating region; and
forming a gate, from a gating material, in the gating region.

10. The method of claim 7 , wherein the protruding structure is formed of dielectric material.

11. The method of claim 7 , wherein the protruding structure is adjacent a nanowire formed by the semiconductor material, the shadow region extending across a width of the nanowire such that a section of the nanowire is not covered by the superconductor material across its entire width, thereby forming a junction between two further sections of the nanowire, both of which are at least partially covered by the superconductor material.

12. The method of claim 7 , wherein the selective area growth phase and the superconductor growth phase are performed in a vacuum chamber, with the substrate remaining in the vacuum chamber and vacuum maintained throughout and in between those phases.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Krogstrup Jeppesen Peter

Classifications

• G06N10/00

  Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D62/119

  Nanowire, nanosheet or nanotube semiconductor bodies · CPC title

• H01L27/18 Primary

  Electricity · mapped topic

• C23C14/28

  by wave energy or particle radiation (C23C14/32 - C23C14/48 take precedence) · CPC title