Array substrate, manufacturing method thereof, and display device

Patent metadata

Field	Value
Publication number	US-11710747-B2
Application number	US-201816340606-A
Country	US
Kind code	B2
Filing date	Sep 29, 2018
Priority date	Oct 11, 2017
Publication date	Jul 25, 2023
Grant date	Jul 25, 2023

Abstract

An array substrate, a manufacturing method thereof and a display device are provided. The array substrate includes: a base substrate; a first electrode located on the base substrate and including a pad portion, the pad portion including a first surface and a second surface, the second surface being closer to the base substrate than the first surface; a first insulation layer located on the first electrode and including a first via hole; a second insulation layer located on the first insulation layer and including a second via hole; and a second electrode located on the second insulation layer; the second electrode is electrically connected with the first electrode at the pad portion through the first via hole and the second via hole, and an orthographic projection of the pad portion on the base substrate falls within an orthographic projection of the second via hole on the base substrate.

First claim

What is claimed is:

1. A manufacturing method of an array substrate, comprising:
forming a first electrode on a base substrate, the first electrode comprising a pad portion, the pad portion comprising a first surface and a second surface intersected with the first surface, the second surface being closer to the base substrate than the first surface;
forming a first insulation film on the first electrode;
forming a first via hole in the first insulation film to form a first insulation layer;
forming a second insulation film on the first insulation film or the first insulation layer;
forming a second via hole in the second insulation film to form a second insulation layer; and
forming a second electrode on the second insulation layer,
wherein the second electrode is electrically connected with the first electrode at the pad portion through the first via hole and the second via hole, and an orthographic projection of the first via hole on the base substrate falls within an orthographic projection of the first surface on the base substrate,
wherein firstly the first via hole is formed in the first insulation film, then the second insulation film is formed on the first insulation layer, and then the second via hole is formed in the second insulation film,
wherein the first via hole and the second via hole are formed by using a same mask.

2. The manufacturing method of the array substrate according to claim 1 , wherein an area of the first via hole is less than an area of the second via hole by adjusting at least one selected from the group consisting of an exposure amount, a development time and an etch parameter.

3. The manufacturing method of the array substrate according to claim 1 , wherein an orthographic projection of the pad portion on the base substrate falls within an orthographic projection of the second via hole on the base substrate.

4. A manufacturing method of an array substrate, comprising:
forming a first electrode on a base substrate, the first electrode comprising a pad portion, the pad portion comprising a first surface and a second surface intersected with the first surface, the second surface being closer to the base substrate than the first surface;
forming a first insulation film on the first electrode;
forming a first via hole in the first insulation film to form a first insulation layer;
forming a second insulation film on the first insulation film or the first insulation layer;
forming a second via hole in the second insulation film to form a second insulation layer; and
forming a second electrode on the second insulation layer,
wherein the second electrode is electrically connected with the first electrode at the pad portion through the first via hole and the second via hole, and an orthographic projection of the first via hole on the base substrate falls within an orthographic projection of the first surface on the base substrate,
wherein firstly the first insulation film and the second insulation film are formed, then the second via hole is formed in the second insulation film, and then the first via hole is formed in the first insulation film,
wherein the manufacturing method of the array substrate further comprises: forming a photoresist film after forming the second via hole; performing a process on the photoresist film to remove a majority of the photoresist to form a photoresist layer, the photoresist layer being at an edge of the second via hole, the photoresist layer having a hollow section corresponding to the first via hole to be formed, etching the first insulation film by using the photoresist layer as a mask; and then removing the photoresist layer to form the first via hole in the first insulation film,
wherein a thickness of the photoresist film is gradually increased in a direction from a central position of the second via hole to an edge position of the second via hole.

5. The manufacturing method of the array substrate according to claim 4 , wherein the photoresist layer at least covers the second surface.

6. The manufacturing method of the array substrate according to claim 4 , wherein a position of the photoresist film with a minimum thickness in the second via hole is closer to the base substrate than a surface of the second insulation layer away from the base substrate.

7. The manufacturing method of the array substrate according to claim 4 , wherein the photoresist layer is located only in the second via hole.

8. An array substrate, comprising:
a base substrate;
a first electrode located on the base substrate and comprising a pad portion, the pad portion comprising a first surface and a second surface intersected with the first surface, the second surface being closer to the base substrate than the first surface;
a first insulation layer located on the first electrode and comprising a first via hole;
a second insulation layer located on the first insulation layer and comprising a second via hole; and
a second electrode located on the second insulation layer,
wherein the second electrode is electrically connected with the first electrode at the pad portion through the first via hole and the second via hole, and an orthographic projection of the first via hole on the base substrate falls within an orthographic projection of the first surface on the base substrate, and
wherein the first via hole is located within the second via hole;
the array substrate further comprises an interlayer dielectric layer disposed between the first electrode and the base substrate, wherein the first electrode further comprises a connection portion, the connection portion and the pad portion are of an integral structure, the connection portion fills in a via hole penetrating the interlayer dielectric layer, and the pad portion is located above the interlayer dielectric layer.

9. The array substrate according to claim 8 , wherein a distance between a bottom end face of the first via hole and the base substrate is greater than a distance between a bottom end face of the second via hole and the base substrate.

10. The array substrate according to claim 9 , wherein a distance between a top end face of the first via hole and the base substrate is less than a distance between a top end face of the second via hole and the base substrate.

11. The array substrate according to claim 8 , wherein an orthographic projection of the pad portion on the base substrate falls within an orthographic projection of the second via hole on the base substrate.

12. The array substrate according to claim 8 , wherein at least the second surface of the first electrode is in contact with the first insulation layer.

13. The array substrate according to claim 8 , wherein a part of the first surface is in contact with the first insulation layer, and an orthographic projection of the part of the first surface on the base substrate is located outside an orthographic projection of the first via hole on the base substrate.

14. The array substrate according to claim 8 , wherein the first electrode is a drain electrode of a thin film transistor, the second electrode is a pixel electrode, the first insulation layer is a buffer passivation layer, and the second insulation layer is a planarization layer.

15. The array substrate according to claim 8 , wherein a material of the second sub-electrode is more easily corroded by a developer than a material of the first sub- electrode and a material of the third sub-electrode.

16. A display device, comprising the array substrate according to claim 8 .

17. The array substrate according to claim 8 , wherein the first electrode com

Assignees

• Ordos Yuansheng Optoelectronics Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Yan Fang
• Shi Dawei
• Yao Lei
• Wang Zifeng
• Wang Wentao
• Yang Lu
• Xu Haifeng
• Si Xiaowen
• Wang Jinfeng
• Yan Lei
• Xue Jinjin
• Hou Lin

Classifications

• H10D86/021

  of multiple TFTs · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H01L27/124 Primary

  Electricity · mapped topic

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title