Metal and spacer patterning for pitch division with multiple line widths and spaces

Patent metadata

Field	Value
Publication number	US-11710636-B2
Application number	US-201816013842-A
Country	US
Kind code	B2
Filing date	Jun 20, 2018
Priority date	Jun 20, 2018
Publication date	Jul 25, 2023
Grant date	Jul 25, 2023

Abstract

Metal spacer-based approaches for fabricating conductive lines/interconnects are described. In an example, an integrated circuit structure includes a substrate. A first spacer pattern is on the substrate, the first spacer pattern comprising a first plurality of dielectric spacers and a first plurality of metal spacers formed along sidewalls of the first plurality of dielectric spacers, wherein the first plurality of dielectric spacers have a first width (W1). A second spacer pattern is on the substrate, where the second spacer pattern interleaved with the first spacer pattern, the second spacer pattern comprising a second plurality of dielectric spacers having a second width (W2) formed on exposed sidewalls of the first plurality of metal spacers, and a second plurality of metal spacers formed on exposed sidewalls of the second plurality of dielectric spacers.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a substrate;
a first spacer pattern on the substrate, the first spacer pattern comprising a first plurality of dielectric spacers and a first plurality of metal spacers formed along sidewalls of the first plurality of dielectric spacers, wherein the first plurality of dielectric spacers have a first width (W 1 ); and
a second spacer pattern on the substrate, the second spacer pattern interleaved with the first spacer pattern, the second spacer pattern comprising a second plurality of dielectric spacers having a second width (W 2 ) formed on exposed sidewalls of the first plurality of metal spacers, and a second plurality of metal spacers formed on exposed sidewalls of the second plurality of dielectric spacers, wherein the interleaved first spacer pattern and the second spacer pattern form respective lines of symmetry centered on the first plurality of dielectric spacers, wherein the lines of symmetry have two sets of dielectric spacers and metal spacers that are left/right symmetric from the lines of symmetry;
wherein the first plurality of dielectric spacers comprise a backbone pattern on which the first plurality of metal spacers are formed, and wherein neither the first plurality of dielectric spacers nor the first plurality of metal spacers are removed and both become part of the integrated circuit.

2. The integrated circuit claim 1 , wherein the first plurality of metal spacers and the second plurality metal spacers have a same width.

3. The integrated circuit claim 1 , wherein the first plurality of metal spacers and the second plurality metal spacers have a different width.

4. The integrated circuit claim 1 , wherein the first plurality of metal spacers and the second plurality metal spacers are formed from a same metal material.

5. The integrated circuit claim 1 , wherein the first plurality of metal spacers and the second plurality metal spacers are formed from a different metal material.

6. The integrated circuit claim 1 , wherein a metal material comprising the first plurality of metal spacers and the second plurality of metal spacers has a property that the metal material can be deposited via atomic layer deposition (ALD) and vertically etched.

7. The integrated circuit claim 6 , wherein the metal material selected from titanium nitride, titanium, tungsten, and alloys thereof.

8. An integrated circuit, comprising:
a substrate;
a first spacer pattern on the substrate, the first spacer pattern comprising a first plurality of dielectric spacers and a first plurality of metal spacers formed along sidewalls of the first plurality of dielectric spacers, wherein the first plurality of dielectric spacers and the first plurality of metal spacers have a first width (W 1 );
a second spacer pattern on the substrate, the second spacer pattern interleaved with the first spacer pattern, the second spacer pattern comprising a second plurality of dielectric spacers having a second width (W 2 ) formed on exposed sidewalls of the first plurality of metal spacers, and a second plurality of metal spacers formed on exposed sidewalls of the second plurality of dielectric spacers; and
a third spacer pattern on the substrate, the third spacer pattern interleaved with the first spacer pattern and the second spacer pattern, the third spacer pattern comprising a third plurality of dielectric spacers formed on exposed sidewalls of the second plurality of metal spacers, and a third plurality of metal spacers formed on exposed sidewalls of the third plurality of dielectric spacers, wherein the third plurality of metal spacers are formed from a metal material different from the first plurality of metal spacers and the second plurality of metal spacers, wherein the interleaved first spacer pattern and the second spacer pattern form respective lines of symmetry centered on the first plurality of dielectric spacers, wherein the lines of symmetry have two sets of dielectric spacers and metal spacers that are left/right symmetric from the lines of symmetry;
wherein the first plurality of dielectric spacers comprise a backbone pattern on which the first plurality of metal spacers are formed, and wherein neither the first plurality of dielectric spacers nor the first plurality of metal spacers are removed and both become part of the integrated circuit.

9. The integrated circuit claim 8 , wherein the first plurality of metal spacers and the second plurality metal spacers are formed from a same metal material.

10. The integrated circuit claim 8 , wherein the first plurality of metal spacers and the second plurality metal spacers are formed from a different metal material.

11. The integrated circuit claim 8 , wherein a metal material comprising the first plurality of metal spacers and the second plurality of metal spacers has a property that the metal material can be deposited via atomic layer deposition (ALD) and vertically etched.

12. The integrated circuit claim 11 , wherein the metal material selected from titanium nitride, titanium, tungsten, and alloys thereof.

13. A method for fabricating a metallization layer of an integrated circuit, comprising:
forming a first spacer pattern over a substrate, the first spacer pattern comprising a first plurality of dielectric spacers and a first plurality of metal spacers formed along sidewalls of the first plurality of dielectric spacers, wherein the first plurality of dielectric spacers have a first width (W 1 ); and
forming a second spacer pattern over the substrate, the second spacer pattern interleaved with the first spacer pattern, the second spacer pattern comprising a second plurality of dielectric spacers having a second width (W 2 ) formed on exposed sidewalls of the first plurality of metal spacers, and a second plurality of metal spacers formed on exposed sidewalls of the second plurality of dielectric spacers, wherein the interleaved first spacer pattern and the second spacer pattern form respective lines of symmetry centered on the first plurality of dielectric spacers, wherein the lines of symmetry have two sets of dielectric spacers and metal spacers that are left/right symmetric from the lines of symmetry;
wherein the first plurality of dielectric spacers comprise a backbone pattern on which the first plurality of metal spacers are formed, and wherein neither the first plurality of dielectric spacers nor the first plurality of metal spacers are removed and both become part of the integrated circuit.

14. The method of claim 13 , further comprising: forming the first plurality of dielectric spacers as the backbone pattern.

15. The method of claim 13 , wherein forming the first plurality of metal spacers further comprises:
depositing a first metal spacer material on the first plurality of dielectric spacers; and
removing the first metal spacer material by a selective vertical etch to form the first plurality of metal spacers along sidewalls of the first plurality of dielectric spacers.

16. The method of claim 13 , wherein forming the second spacer pattern further comprises: depositing a second dielectric spacer material on the first spacer pattern and removing the second dielectric spacer material to form the second plurality of dielectric spacers along exposed sidewalls of the first plurality of metal spacers.

17. The method of claim 13 , wherein forming the second plurality of metal spacers further comprises:
depositing a second metal spacer material over the substrate; and
removing the second metal spacer material by a selective vertical etch to form the second plurality of metal spac

Assignees

• Intel Corp

Inventors

• Lin Kevin
• Wallace Charles

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P14/43

  Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

• H10W20/01

  Manufacture or treatment · CPC title