Multilayer ceramic capacitor
US-2019371526-A1 · Dec 5, 2019 · US
Ceramic electronic device and manufacturing method of the same
US11710601B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11710601-B2 |
| Application number | US-202117372401-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 9, 2021 |
| Priority date | Oct 30, 2020 |
| Publication date | Jul 25, 2023 |
| Grant date | Jul 25, 2023 |
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- Title
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- Abstract
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- CPC / IPC classifications
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Abstract
Official abstract text for this publication.
A ceramic electronic device includes a multilayer chip in which a plurality of dielectric layers of which a main component is ceramic and a plurality of internal electrode layers are stacked. The plurality of internal electrode layers include Ni, Sn and Au.
First claim
Opening claim text (preview).
What is claimed is: 1. A ceramic electronic device comprising: a multilayer chip in which a plurality of dielectric layers of which a main component is ceramic and a plurality of internal electrode layers are stacked, wherein the plurality of internal electrode layers include Ni, Sn and Au, and wherein an Au concentration near each interface between the plurality of internal electrode layers and the plurality of dielectric layers is larger than the Au concentration in each center portion in a thickness direction in the plurality of internal electrode layers. 2. The ceramic electronic device as claimed in claim 1 , wherein a total amount of Sn and Au with respect to Ni in the plurality of internal electrode layers is 0.01 at % or more and 95 at % or less. 3. The ceramic electronic device as claimed in claim 2 , wherein the total amount of Sn and Au with respect to Ni in the plurality of internal electrode layers is 0.2 at % or more and 10 at % or less. 4. The ceramic electronic device as claimed in claim 1 , wherein an amount of Au is smaller than an amount of Sn in the plurality of internal electrode layers. 5. The ceramic electronic device as claimed in claim 1 , wherein a Sn concentration near each interface between the plurality of internal electrode layers and the plurality of dielectric layers is larger than the Sn concentration in each center portion in a thickness direction in the plurality of internal electrode layers.
Assignees
Inventors
Classifications
- H01G4/30Primary
Stacked capacitors (H01G4/33 takes precedence) · CPC title
- C04B35/4682Primary
based on BaTiO3 perovskite phase · CPC title
- H01G4/008Primary
Selection of materials · CPC title
Form of non-self-supporting electrodes · CPC title
based on titanium oxides or titanates (H01G4/1245 takes precedence) · CPC title
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Frequently asked questions
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- What does patent US11710601B2 cover?
- A ceramic electronic device includes a multilayer chip in which a plurality of dielectric layers of which a main component is ceramic and a plurality of internal electrode layers are stacked. The plurality of internal electrode layers include Ni, Sn and Au.
- Who is the assignee on this patent?
- Taiyo Yuden Kk
- What technology area does this patent fall under?
- Primary CPC classification H01G4/30. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jul 25 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).