Position-based rendering apparatus and method for multi-die/GPU graphics processing

Patent metadata

Field	Value
Publication number	US-11710269-B2
Application number	US-202217876358-A
Country	US
Kind code	B2
Filing date	Jul 28, 2022
Priority date	Aug 29, 2018
Publication date	Jul 25, 2023
Grant date	Jul 25, 2023

Abstract

Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

First claim

What is claimed is:

1. A method comprising:
dividing an image frame into a plurality of tiles;
assigning a non-overlapping subset of the tiles to each of a plurality of graphics processors, wherein each of the graphics processors is integrated on a separate semiconductor die and comprises a graphics pipeline for rendering the assigned subset of tiles;
distributing a plurality of graphics draws to the plurality of graphics processors, wherein each of the graphics processors is assigned a subset of the plurality of graphics draws;
generating, at each of the graphics processors, visibility data for each of the plurality of tiles of the image frame or a subset thereof using vertex data associated with the subset of graphics draws to which the graphics processor is assigned;
distributing different subsets of the visibility data to different graphics processors located on different semiconductor dies, wherein each of the graphics processers is to receive a subset of the visibility data for the tiles on which the graphic processor is to perform geometry work;
limiting geometry work to be performed on the tiles assigned to each graphics processor using the subset of the visibility data received by each of the graphics processors;
rendering the assigned subset of tiles at each graphics processor to generate rendered tiles; and
combining the rendered tiles to generate a complete image frame.

2. The method of claim 1 , wherein generating the visibility data comprises:
comparing primitives included in the vertex data for each of the tiles to identify one or more primitives which are visible within the tile's region; and
identifying occluded primitives in the visibility data.

3. The method of claim 2 , wherein limiting the geometry work comprises performing geometry work using only primitives that are visible based on the visibility data.

4. The method of claim 2 , further comprising:
rasterizing the subsets of tiles by each respective graphics processor to generate pixels for each tile of each subset of tiles.

5. The method of claim 4 , further comprising:
performing pixel shading operations on each tile within each subset by each respective graphics processor to generate final pixels for each tile.

6. The method of claim 5 , further comprising:
combining the final pixels for each tile within a frame buffer of at least one of the plurality of graphics processors.

7. The method of claim 1 , wherein the visibility data is generated responsive to performance of position-only shading at each of the graphics processors using the vertex data associated with the subset of graphics draws assigned to the graphics processor.

8. A graphics processing apparatus comprising:
a plurality of graphics processors, each integrated on a separate semiconductor die;
an interconnect to couple the plurality of graphics processors; and
a graphics driver to assign a different subset of a plurality of graphics draws to each of the graphics processors, each graphics draw associated with one or more of a plurality of tiles of an image frame;
wherein each graphics processor is assigned a non-overlapping subset of the tiles to be rendered by a graphics pipeline of the graphics processor;
wherein each graphics processor is to generate visibility data for each of the plurality of tiles of the image frame or a subset thereof using vertex data associated with the subset of graphics draws to which the graphics processor is assigned;
wherein the interconnect is to distribute different subsets of the visibility data to different graphics processors, each of the graphics processers to receive a subset of the visibility data for the tiles on which the graphic processor is to perform geometry work;
wherein each graphics processor is to limit geometry work to be performed on the tiles assigned to the graphics processor using the subset of the visibility data received via the interconnect;
wherein the graphics pipeline of each graphics processor is to render the assigned subset of tiles to generate rendered tiles which are combined to generate a complete image frame.

9. The graphics processing apparatus of claim 8 , wherein each graphics processing apparatus is to generate the visibility data by:
comparing primitives included in the vertex data for each of the tiles to identify one or more primitives which are visible within the tile's region; and
identifying occluded primitives in the visibility data.

10. The graphics processing apparatus of claim 9 , wherein each graphics processor is to limit geometry work by performing geometry work using only primitives that are visible based on the visibility data.

11. The graphics processing apparatus of claim 9 , wherein the graphics pipeline of each graphics processor is to rasterize the subsets of tiles assigned to the graphics processor to generate pixels for each tiles in the subset.

12. The graphics processing apparatus of claim 11 , wherein the graphics pipeline of each graphics processor is to perform pixel shading operations on each tile in the subset to generate final pixels for each tile.

13. The graphics processing apparatus of claim 12 , further comprising a frame buffer to combine the final pixels for each tile rendered by the plurality of graphics processors.

14. The graphics processing apparatus of claim 8 , wherein each of the graphics processors is to perform position-only shading using the vertex data associated with the subset of graphics draws to which the graphics processor is assigned to generate the visibility data.

15. A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform operations of:
dividing an image frame into a plurality of tiles;
assigning a non-overlapping subset of the tiles to each of a plurality of graphics processors, wherein each of the graphics processors is integrated on a separate semiconductor die and comprises a graphics pipeline for rendering the assigned subset of tiles;
distributing a plurality of graphics draws to the plurality of graphics processors, wherein each of the graphics processors is assigned a subset of the plurality of graphics draws;
generating, at each of the graphics processors, visibility data for each of the plurality of tiles of the image frame or a subset thereof using vertex data associated with the subset of graphics draws to which the graphics processor is assigned;
distributing different subsets of the visibility data to different graphics processors located on different semiconductor dies, wherein each of the graphics processers is to receive a subset of the visibility data for the tiles on which the graphic processor is to perform geometry work;
limiting geometry work to be performed on the tiles assigned to each graphics processor using the subset of the visibility data received by each of the graphics processors;
rendering the assigned subset of tiles at each graphics processor to generate rendered tiles; and
combining the rendered tiles to generate a complete image frame.

16. The non-transitory machine-readable medium of claim 15 , wherein generating the visibility data comprises:
comparing primitives included in the vertex data for each of the tiles to identify one or more primitives which are visible within the tile's region; and
identifying occluded primitives in the visibility data.

17. The non-transitory machine-readable medium of claim 16 , wherein limiting the geometry work comprises performing geometry work using only primitives that are visible based on the visibility data.

Assignees

• Intel Corp

Inventors

• Schluessler Travis
• Waters Zack
• Apodaca Michael
• Johnston Daniel
• Surprise Jason
• Surti Prasoonkumar
• Maiyuran Subramaniam
• Doyle Peter
• Sharma Saurabh
• Shah Ankur
• Ramadoss Murali

Classifications

• G06T15/005 Primary

  General purpose rendering architectures · CPC title

• G06T15/40

  Hidden part removal · CPC title

• G06T15/80

  Shading · CPC title

• G06T2210/52

  Parallel processing · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title