Semiconductor device having integrated antenna and method therefor

Patent metadata

Field	Value
Publication number	US-11705410-B2
Application number	US-202017119846-A
Country	US
Kind code	B2
Filing date	Dec 11, 2020
Priority date	Dec 11, 2020
Publication date	Jul 18, 2023
Grant date	Jul 18, 2023

Abstract

A semiconductor device having an integrated antenna is provided. The semiconductor device includes a base die having an integrated circuit formed at an active surface and a cap die bonded to the backside surface of the base die. A metal trace is formed over a top surface of the cap die. A cavity is formed under the metal trace. A conductive via is formed through the base die and the cap die interconnecting the metal trace and a conductive trace of the integrated circuit.

First claim

What is claimed is:

1. A semiconductor device comprising:
a base die having an active surface and a backside surface, an integrated circuit formed at the active surface;
a cap die having a top surface and a bottom surface, the bottom surface of the cap die bonded to the backside surface of the base die;
a metal trace formed over the top surface of the cap die;
a dielectric layer disposed between the metal trace and the top surface of the cap die;
a conductive via formed through the base die and the cap die, the conductive via interconnecting the metal trace and a conductive trace of the integrated circuit; and
a cavity formed under the metal trace, a portion of the cap die remaining between the metal trace and the cavity.

2. The semiconductor device of claim 1 , further comprising a metal layer formed on sidewall surfaces and a bottom surface of the cavity.

3. The semiconductor device of claim 1 , wherein the metal trace is configured and arranged as an antenna coupled to the integrated circuit by way of the conductive via.

4. The semiconductor device of claim 3 , wherein a bottom surface of the cavity is separated from the antenna by a predetermined distance, the predetermined distance sufficient for propagation of a mmWave signal.

5. The semiconductor device of claim 1 , wherein the cavity is formed in the cap die before the cap die is bonded to the base die.

6. The semiconductor device of claim 1 , wherein the conductive via is formed as a coaxial connection between the metal trace and the conductive trace of the integrated circuit.

7. The semiconductor device of claim 1 , further comprising a plurality of bond pads formed on the active surface of the base die, the plurality of bond pads configured for connection to a package substrate.

8. The semiconductor device of claim 7 , wherein the plurality of bond pads is connected to the package substrate by way of copper pillars or solder bumps.

9. A method comprising:
forming a cavity in a cap die;
forming a metal trace over a top surface of the cap die and the cavity, a portion of the cap die located between the metal trace and the cavity, a dielectric layer disposed between the metal trace and the top surface of the cap die;
bonding a bottom surface of the cap die with a backside surface of a base die, the base die including an integrated circuit formed at an active surface; and
interconnecting the metal trace and a conductive trace of the integrated circuit by way of a through via formed through the cap die and the base die.

10. The method of claim 9 , further comprising forming a metal layer on sidewall surfaces and a bottom surface of the cavity.

11. The method of claim 9 , wherein the metal trace is configured and arranged as an antenna coupled to the integrated circuit by way of the through via.

12. The method of claim 9 , further comprising depositing the dielectric layer on the top surface of the cap die before forming the metal trace.

13. The method of claim 9 , further comprising filling the cavity with a quartz glass material.

14. The method of claim 9 , wherein the through via is formed as a coaxial connection between the metal trace and the conductive trace of the integrated circuit.

15. The method of claim 9 , further comprising forming a plurality of conductive connectors on a respective plurality of bond pads at the active surface of the base die, the plurality of conductive connectors configured and arranged for interconnecting the integrated circuit with a printed circuit board or a package substrate.

16. A semiconductor device comprising:
a base die having an active surface and a backside surface, an integrated circuit formed at the active surface;
a cap die having a top surface and a bottom surface, the bottom surface of the cap die bonded to the backside surface of the base die;
an antenna formed over the top surface of the cap die;
a dielectric layer disposed between the antenna and the top surface of the cap die;
a conductive via formed through the base die and the cap die, the conductive via interconnecting the antenna and a conductive trace of the integrated circuit; and
a cavity formed under the antenna, a portion of the cap die remaining between the metal trace and the cavity.

17. The semiconductor device of claim 16 , further comprising a metal layer formed on sidewall surfaces and a bottom surface of the cavity.

18. The semiconductor device of claim 16 , wherein a bottom surface of the cavity is separated from the antenna by a predetermined distance, the predetermined distance sufficient for propagation of a mmWave signal.

19. The semiconductor device of claim 16 , wherein the conductive via is formed as a coaxial connection between the antenna and the conductive trace of the integrated circuit.

20. The semiconductor device of claim 16 , wherein the cavity is filled with a quartz glass material.

Assignees

• Nxp Usa Inc

Inventors

• Vincent Michael B
• Gupta Vivek
• Gan Richard Te
• Mirpuri Kabir

Classifications

• H10W70/6528

  of the portions that connect to chips, wafers or package parts · CPC title

• H10W44/248

  for antennas · CPC title

• H10W44/212

  Coaxial feed-throughs in substrates · CPC title

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W74/016

  using moulds · CPC title