Methods to generate a wiring schema

Patent metadata

Field	Value
Publication number	US-11704451-B2
Application number	US-202217583720-A
Country	US
Kind code	B2
Filing date	Jan 25, 2022
Priority date	Jul 10, 2019
Publication date	Jul 18, 2023
Grant date	Jul 18, 2023

Abstract

Apparatus and associated methods relate to generating a wiring schema with more than one safety device sharing at least one test signal through one or more external terminal blocks when the number of terminals required by safety devices exceeds the number of available terminals of a safety controller. In an illustrative example, the method may include determining a total number of terminals A of safety devices to be connected to a safety evaluation device having a number of terminals B. If A is greater than B, the method may then include generating a wiring schema that one or more external terminal blocks may show indicia of electrical connections between an identified set of safety devices and a shared terminal of the safety evaluation device associated with that set. Various embodiments may advantageously expand a number of devices to be connected to the safety evaluation device.

First claim

What is claimed is:

1. A computer program product (CPP) comprising a program of instructions tangibly embodied on a non-transitory computer readable medium wherein, when the instructions are executed on a processor, the processor causes operations to be performed to generate a wiring schema, the operations comprising:
receive a first data of a number of terminals A of N safety devices to be connected to a safety evaluation device;
receive a second data of a number of terminals B of the safety evaluation device available to connect to the N safety devices;
determine whether A is greater than B; and,
upon determining A is greater than B, then:
identify at least one set of the N safety devices that is able to share a terminal of the safety evaluation device based upon test signal compatibility among the N safety devices;
generate a wiring schema, wherein, for each of the identified at least one set, an external terminal block provides electrical connection between each of the safety devices in that set and the shared terminal of the safety evaluation device associated with that set;
for each of the identified at least one set of the N safety devices, determine a shared terminal of the safety evaluation device connectable to the external terminal block; and,
generate a signal such that a user interface is presented to a user, the user interface comprising a human-readable wiring schema.

2. The CPP of claim 1 , wherein generate a wiring schema comprises generating a plurality of wiring schema.

3. The CPP of claim 2 , wherein the plurality of wiring schema is generated based on inventory available of the external terminal block.

4. The CPP of claim 2 , wherein the plurality of wiring schema is generated based on a price of the external terminal block.

5. The CPP of claim 2 , wherein:
the operations further comprise: generate a signal such that a user interface is presented to a user, the user interface comprising a human-readable wiring schema, and,
the signal is further generated such that the user interface comprises at least one indicia prompting a user to provide input corresponding to a selection of at least one of the plurality of wiring schema.

Assignees

• Banner Eng

Inventors

• Klesk John
• Liu Danielle
• Sorvari Greg
• Erickson Dean
• Anderson Greg
• Dixon Jeff

Classifications

• G06F30/13 Primary

  Architectural design, e.g. computer-aided architectural design [CAAD] related to design of buildings, bridges, landscapes, production plants or roads · CPC title

• G06F30/12

  characterised by design entry means specially adapted for CAD, e.g. graphical user interfaces [GUI] specially adapted for CAD · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• G06F30/333

  Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] · CPC title

• G06F30/20 Primary

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title