Active-active storage system and address assignment method

Patent metadata

Field	Value
Publication number	US-11704243-B2
Application number	US-202217977144-A
Country	US
Kind code	B2
Filing date	Oct 31, 2022
Priority date	Oct 25, 2017
Publication date	Jul 18, 2023
Grant date	Jul 18, 2023

Abstract

A method of labeling logic number units in a storage system results in the use of the same label for related LUNs in different storage arrays. A first storage array includes a first source logical unit number LUN, the second storage array includes a first target LUN, and the first source LUN and the first target LUN are a pair of active-active LUNs. The first storage array sends an assignable-address set of selectable labels for the first source LUN to the address assignment apparatus. The second storage array sends an assignable-address set of selectable labels for the first target LUN to the address assignment apparatus. The address assignment apparatus selects a label that is in both assignable-address sets of the first source LUN and first target LUN, and assign that selected label to both LUNs. Thereafter, the address assignment apparatus sends the selected label to the first storage array and the second storage array for identifying both the first source LUN and the first target LUN.

First claim

What is claimed is:

1. A storage system comprising:
a first storage array comprising a first logical unit number (LUN);
a second storage array comprising a second LUN, wherein the first LUN and the second LUN form a pair of active-active LUNs; and
an address assignment apparatus,
wherein the first storage array is configured to send a plurality of assignable address labels for the first LUN to the address assignment apparatus,
wherein the second storage array is configured to send a plurality of assignable address labels for the second LUN to the address assignment apparatus,
wherein the address assignment apparatus is configured to:
select an assignable address label for both the first LUN and the second LUN, the selected assignable address label being located in both the assignable address labels for the first LUN and the assignable address labels for the second LUN;
send the selected assignable address label to the first storage array as a label for identifying the first LUN; and
send the selected assignable address label to the second storage array as a label for identifying the second LUN.

2. The storage system according to claim 1 , wherein
the address assignment apparatus is further configured to:
send a first address query command to the first storage array to query the plurality of assignable address labels for the first LUN; and
send a second address query command to the second storage array to query the plurality of assignable address labels for the second LUN.

3. The storage system according to claim 1 , wherein
the first storage array is further configured to generate the plurality of assignable address labels for the first LUN; and
the second storage array is further configured to generate the plurality of assignable address labels for the second LUN.

4. The storage system according to claim 1 , wherein the storage system comprises a host, and the address assignment apparatus is located in a host.

5. An address assignment apparatus comprising:
an interface configured for communicating with a first storage array and a second storage array, wherein the first storage array comprises a first logical unit number (LUN), the second storage array comprises a second LUN, wherein the first LUN and the second LUN form a pair of active-active LUNs; and
a processor configured to:
receive, via the interface, assignable address labels for the first LUN sent by the first storage array;
receive, via the interface, assignable address labels for the first LUN sent by the second storage array;
select an assignable address label for both the first LUN and the second LUN, the selected assignable address label being located in both the assignable address labels for the first LUN and the assignable address labels for the second LUN;
send the selected assignable address label to the first storage array as a label for identifying the first LUN; and
send the selected assignable address label to the second storage array as a label for identifying the second LUN.

6. The address assignment apparatus according to claim 5 , wherein the processor is further configured to:
send a first address query command to the first storage array to query the assignable address labels for the first LUN; and
send a second address query command to the second storage array to query the assignable address labels for the second LUN.

7. An address assignment method performed by an address assignment apparatus in a storage system, comprising:
receiving, from a first storage array in the storage system, assignable address labels for a first logical unit number (LUN) of the first storage array;
receiving, from a second storage array in the storage system, assignable address labels for a second LUN of the second storage array, wherein the first LUN and the second LUN form a pair of active-active LUNs;
selecting an assignable address label for both the first LUN and the second LUN, the selected assignable address label being located in both the assignable address labels for the first LUN and the assignable address labels for the second LUN;
sending the selected assignable address label to the first storage array as a label for identifying the first LUN; and
sending the selected assignable address label to the second storage array as a label for identifying the second LUN.

8. The method according to claim 7 , further comprising:
sending a first address query command to the first storage array to query the assignable address labels for the first LUN; and
sending a second address query command to the second storage array to query the assignable address labels for the second LUN.

Assignees

• Huawei Tech Co Ltd

Inventors

• Li Tiande
• Li Langbo

Classifications

• G06F12/0646 Primary

  Configuration or reconfiguration · CPC title

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title

• G06F2009/45583

  Memory management, e.g. access or allocation · CPC title

• G06F3/0614 Primary

  Improving the reliability of storage systems · CPC title

• G06F12/00

  Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) · CPC title