Expansion of packet data within processing pipeline

Patent metadata

Field	Value
Publication number	US-11700212-B2
Application number	US-202117494515-A
Country	US
Kind code	B2
Filing date	Oct 5, 2021
Priority date	Sep 28, 2017
Publication date	Jul 11, 2023
Grant date	Jul 11, 2023

Abstract

Some embodiments provide a network forwarding IC with packet processing pipelines, at least one of which includes a parser, a set of match-action stages, and a deparser. The parser is configured to receive a packet and generate a PHV including a first number of data containers storing data for the packet. A first match-action stage is configured to receive the PHV from the parser and expand the PHV to a second, larger number of data containers storing data for the packet. Each of a set of intermediate match-action stage is configured to receive the expanded PHV from a previous stage and provide the expanded PHV to a subsequent stage. A final match-action stage is configured to receive the expanded PHV and reduce the PHV to the first number of data containers. The deparser is configured to receive the reduced PHV from the final match-action stage and reconstruct the packet.

First claim

The invention claimed is:

1. An integrated circuit for use in network packet forwarding, the integrated circuit comprising:
configurable packet processing circuitry to receive at least one packet, the at least one packet comprising header fields, the configurable packet processing circuitry being configurable, when the integrated circuit is in operation, to comprise a plurality of packet processing stages, the plurality of packet processing stages comprising:
at least one parser stage to identify the header fields, the at least one parser stage also to store, in data containers, header field data of the header fields, the data containers belonging to a plurality of data container types, the plurality of data container types comprising at least one data container type and at least one other data container type, the at least one data container type and the at least one other data container type having two different sizes and being configurable based upon parameters specified in compiled program instructions to be received by the integrated circuit; and
match-action stages to modify at least certain of the header field data;

wherein:
the plurality of data container types comprises another data container type whose stored data is unavailable for modification by the match-action stages; and
at least a portion of the header field data is to be stored in the another data container type.

2. The integrated circuit of claim 1 , wherein:
the plurality of packet processing stages also comprises at least one other stage for use in generating at least one egress packet, based upon modified header field data from the match-action stages.

3. The integrated circuit of claim 2 , wherein:
the match-action stages also implement table data look up operations involving the at least certain of the header field data.

4. The integrated circuit of claim 3 , wherein:
the configurable packet processing circuitry is configurable, when the integrated circuit is in the operation, to comprise at least one configurable packet processing pipeline that comprises the plurality of packet processing stages; and
the integrated circuit also comprises packet traffic management, queuing, and shared buffering circuitry between certain stages of the plurality of packet processing stages.

5. The integrated circuit of claim 4 , wherein:
the at least one configurable packet processing pipeline comprises a plurality of configurable packet processing pipelines; and
the plurality of configurable packet processing pipelines comprise at least one ingress pipeline and at least one egress pipeline.

6. The integrated circuit of claim 5 , wherein:
the compiled program instructions are to be received by the integrated circuit, when the integrated circuit is in the operation, from a controller associated with a remote control plane.

7. The integrated circuit of claim 6 , wherein:
the compiled program instructions are to be generated by a compiler based upon at least one P4 program.

8. The integrated circuit of claim 7 , wherein:
the data containers are associated, at least in part, with packet header vector data that is to be provided to the plurality of packet processing stages.

9. One or more non-transient computer readable media storing instructions for being executed by an integrated circuit, the integrated circuit being for use in network packet forwarding, the instructions when executed by the integrated circuit resulting in the integrated circuit being configured to perform operations comprising:
receiving, by configurable packet processing circuitry of the integrated circuit, at least one packet, the at least one packet comprising header fields, the configurable packet processing circuitry being configurable, when the integrated circuit is in operation, to comprise a plurality of packet processing stages, the plurality of packet processing stages comprising at least one parser stage and match-action stages;
identifying, by the at least one parser stage, the header fields;
storing, by the at least one parser stage, in data containers, header field data of the header fields, the data containers belonging to a plurality of data container types, the plurality of data container types comprising at least one data container type and at least one other data container type, the at least one data container type and the at least one other data container type having two different sizes and being configurable based upon parameters specified in compiled program instructions to be received by the integrated circuit; and
modifying, by the match-action stages, at least certain of the header field data;
wherein:
the plurality of data container types comprises another data container type whose stored data is unavailable for modification by the match-action stages; and
at least a portion of the header field data is to be stored in the another data container type.

10. The one or more non-transient computer readable media of claim 9 , wherein:
the plurality of packet processing stages also comprises at least one other stage for use in generating at least one egress packet, based upon modified header field data from the match-action stages.

11. The one or more non-transient computer readable media of claim 10 , wherein:
the match-action stages also implement table data look up operations involving the at least certain of the header field data.

12. The one or more non-transient computer readable media of claim 11 , wherein:
the configurable packet processing circuitry is configurable, when the integrated circuit is in the operation, to comprise at least one configurable packet processing pipeline that comprises the plurality of packet processing stages; and
the integrated circuit also comprises packet traffic management, queuing, and shared buffering circuitry between certain stages of the plurality of packet processing stages.

13. The one or more non-transient computer readable media of claim 12 , wherein:
the at least one configurable packet processing pipeline comprises a plurality of configurable packet processing pipelines; and
the plurality of configurable packet processing pipelines comprise at least one ingress pipeline and at least one egress pipeline.

14. The one or more non-transient computer readable media of claim 13 , wherein:
the compiled program instructions are to be received by the integrated circuit, when the integrated circuit is in the operation, from a controller associated with a remote control plane.

15. The one or more non-transient computer readable media of claim 14 , wherein:
the compiled program instructions are to be generated by a compiler based upon at least one P4 program.

16. The one or more non-transient computer readable media of claim 15 , wherein:
the data containers are associated, at least in part, with packet header vector data that is to be provided to the plurality of packet processing stages.

17. A method implemented using an integrated circuit, the integrated circuit being for use in network packet forwarding, the method comprising:
receiving, by configurable packet processing circuitry of the integrated circuit, at least one packet, the at least one packet comprising header fields, the configurable packet processing circuitry being configurable, when the integrated circuit is in operation, to comprise a plurality of packet processing stages, the plurality of packet processing stages comprising at least one parser stage and match-action stages;
identifying, by the at least one parser stage, the header fields;
storing, by the at least one parser stage,

Assignees

• Barefoot Networks Inc

Inventors

• Bosshart Patrick
• Peterson Jay Evan Scott
• Ferrara Michael Gregory
• Attig Michael E

Classifications

• H04L49/109

  Integrated on microchip, e.g. switch-on-chip · CPC title

• H04L49/3063 Primary

  Pipelined operation · CPC title

• H04L45/7453

  using hashing · CPC title

• H04L45/745

  Address table lookup; Address filtering · CPC title

• H04L47/2441

  relying on flow classification, e.g. using integrated services [IntServ] · CPC title