Passive sample-and-hold analog-to-digital converter with split reference voltage

Patent metadata

Field	Value
Publication number	US-11700006-B2
Application number	US-202117514432-A
Country	US
Kind code	B2
Filing date	Oct 29, 2021
Priority date	Oct 29, 2021
Publication date	Jul 11, 2023
Grant date	Jul 11, 2023

Abstract

An analog-to-digital converter (ADC) circuit comprises one or more most-significant-bit (MSB) capacitors having first ends connected to a voltage comparator and one or more least-significant-bit (LSB) capacitors having first ends connected to the comparator. The circuit further comprises a first switching circuit for each MSB capacitor, configured to selectively connect the second end of the respective MSB capacitor to (a) an input voltage, for sampling, (b) a ground reference, during portions of a conversion phase, and (c) a first conversion reference voltage, for other portions of the conversion phase. The circuit still further comprises a second switch circuit, for each LSB capacitor, configured to selectively connect the second end of the respective LSB capacitor between (d) the ground reference, during portions of the conversion phase, and (e) a second conversion reference voltage, for other portions of the conversion phase, the second conversion reference voltage differing from the first.

First claim

The invention claimed is:

1. A successive-approximation analog-to-digital converter (ADC) circuit, comprising:
a voltage comparator;
one or more most-significant-bit (MSB) capacitors, each having a first end connected to an input of the comparator;
one or more least-significant-bit (LSB) capacitors, each having a first end connected to the input of the comparator;
one or more first switch devices corresponding to each MSB capacitor and configured to selectively connect the second end of the respective MSB capacitor to (a) an input voltage, for the duration of a sampling phase, (b) a ground reference, during portions of a conversion phase, and (c) a first conversion reference voltage for other portions of the conversion phase; and
one or more second switch devices corresponding to each LSB capacitor and configured to selectively connect the second end of the respective LSB capacitor between (d) the ground reference, during portions of the conversion phase, and (e) a second conversion reference voltage, for other portions of the conversion phase, the second conversion reference voltage differing from the first conversion reference voltage;

wherein the comparator, the one or more second switch devices, and a source for the second conversion reference voltage are contained in an integrated circuit, the source for the first conversion reference voltage being external to the integrated circuit.

2. The successive-approximation ADC circuit of claim 1 , wherein the one or more second switch devices are further configured to selectively connect the second end of the respective LSB capacitor to the ground reference during the sampling phase.

3. The successive-approximation ADC circuit of claim 1 , wherein the one or more second switch devices are further configured to selectively connect the second end of the respective LSB capacitor to the input voltage during the sampling phase.

4. The successive-approximation ADC circuit of claim 1 , wherein the one or more first switch devices are external to the integrated circuit.

5. The successive-approximation ADC circuit of claim 1 , wherein the capacitances of the MSB capacitors and the LSB capacitors follow a binary weighting pattern except that the capacitances of the MSB capacitors are each scaled, relative to the capacitances of the LSB capacitors, according to the ratio of the second conversion reference voltage to the first conversion reference voltage.

6. The successive-approximation ADC circuit of claim 1 , further comprising:
a gain correction capacitor having a first end connected to the input of the comparator; and
one or more third switch devices arranged to selectively connect the second end of the gain correction capacitor to the input voltage, for the duration of the sampling phase, and to the ground reference, during the conversion phase.

7. The successive-approximation ADC circuit of claim 1 , further comprising at least one isolation switch configured so that the first end of each MSB capacitor is connected to the input of the comparator via the at least one isolation switch.

8. The successive-approximation ADC circuit of claim 1 , further comprising a digital-to-analog converter (DAC) circuit configured to generate the second conversion reference voltage, responsive to a calibration input.

9. The successive-approximation ADC circuit of claim 1 , further comprising a switched-capacitor amplifier configured to generate the second conversion reference voltage.

10. The successive-approximation ADC circuit of claim 9 , wherein an input capacitance of the switched-capacitor amplifier or a feedback capacitance of the switched-capacitor amplifier, or both, is/are adjustable, so as to control the second conversion reference voltage.

11. The successive-approximation ADC circuit of claim 1 , wherein the one or more LSB capacitors consist of a redundant LSB capacitor array, the capacitors of the redundant LSB capacitor array having capacitances such that a successive-approximation search window provided by the redundant LSB capacitor array is greater than a residual search window provided by the one or more MSB capacitors.

12. A successive-approximation analog-to-digital converter (ADC) circuit, comprising:
a voltage comparator;
one or more sample capacitors, each having a first end connected to an input of the comparator;
one or more most-significant-bit (MSB) digital-to-analog converter (DAC) capacitors, each having a first end connected to an input of the comparator;
one or more least-significant-bit (LSB) DAC capacitors, each having a first end connected to the input of the comparator;
one or more first switch devices corresponding to each sample capacitor and configured to selectively connect the second end of the respective sample capacitor to (a) an input voltage, for the duration of a sampling phase, and (b) a ground reference, during portions of a conversion phase;
one or more second switch devices corresponding to each MSB capacitor and configured to selectively connect the second end of the respective MSB capacitor to (c) the ground reference, during portions of a conversion phase, and (d) a first conversion reference voltage for other portions of the conversion phase; and
one or more third switch devices corresponding to each LSB capacitor and configured to selectively connect the second end of the respective LSB capacitor between (e) the ground reference, during portions of the conversion phase, and (f) a second conversion reference voltage, for other portions of the conversion phase, the second conversion reference voltage differing from the first conversion reference voltage.

13. The successive-approximation ADC circuit of claim 12 , wherein the one or more third switch devices are further configured to selectively connect the second end of the respective LSB capacitor to the ground reference during the sampling phase.

14. The successive-approximation ADC circuit of claim 12 , wherein the one or more third switch devices are further configured to selectively connect the second end of the respective LSB capacitor to the input voltage during the sampling phase.

15. The successive-approximation ADC circuit of claim 12 , wherein the comparator, the one or more third switch devices, and a source for the second conversion reference voltage are contained in an integrated circuit, the one or more second switch devices and a source for the first conversion reference voltage being external to the integrated circuit.

16. The successive-approximation ADC circuit of claim 12 , wherein the capacitances of the MSB capacitors and the LSB capacitors follow a binary weighting pattern except that the capacitances of the MSB capacitors are each scaled, relative to the capacitances of the LSB capacitors, according to the ratio of the second conversion reference voltage to the first conversion reference voltage.

17. The successive-approximation ADC circuit of claim 12 , further comprising at least one isolation switch configured so that the first end of each MSB capacitor is connected to the input of the comparator via the at least one isolation switch.

18. The successive-approximation ADC circuit of claim 12 , further comprising a digital-to-analog converter (DAC) circuit configured to generate the second conversion reference voltage, responsive to a calibration input.

19. The successive-approximation ADC circuit o of claim 12 , further comprising a switched-capacitor amplifier configured to generate the second conversion reference voltage.

20. The successive-approximation

Assignees

• Infineon Technologies Ag

Inventors

• Bogner Peter

Classifications

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/466

  using switched capacitors · CPC title

• H03M1/1009 Primary

  Calibration · CPC title

• H03M1/145

  the steps being performed sequentially in series-connected stages (H03M1/141, H03M1/143, H03M1/16 take precedence) · CPC title

• H03M1/124

  Sampling or signal conditioning arrangements specially adapted for A/D converters · CPC title