Signal sampling with offset calibration

Patent metadata

Field	Value
Publication number	US-11699993-B2
Application number	US-202117395069-A
Country	US
Kind code	B2
Filing date	Aug 5, 2021
Priority date	Sep 15, 2020
Publication date	Jul 11, 2023
Grant date	Jul 11, 2023

Abstract

Methods, systems, and devices for signal sampling with offset calibration are described. For example, sampling circuitry may include an input pair of transistors where input signals may be provided to gate nodes of the transistors, and an output signal may be generated based on a comparison of voltages of drain nodes of the transistors. In some examples, source nodes of the transistors may be coupled with each other, such as via a resistance, and each source node may be configured to be coupled with a ground node. In some examples, a conductive path between the source nodes may be coupled with one or more switching components configurable for further coupling of the source nodes with the ground node. In some examples, enabling such switching components may add an electrical characteristic (e.g., capacitance) to the conductive path between the source nodes, which may be configurable to mitigate sampling circuitry imbalances.

First claim

What is claimed is:

1. An apparatus, comprising:
a first input node coupled with a gate of a first transistor;
a second input node coupled with a gate of a second transistor;
circuitry coupled with a drain node of the first transistor and a drain node of the second transistor and configured to generate an output signal based at least in part on a voltage of the first input node and a voltage of the second input node;
a resistor coupling a source node of the first transistor with a source node of the second transistor;
a first switching circuit configurable to couple the source node of the first transistor with a voltage source based at least in part on a clock signal; and
a second switching circuit configurable to couple the source node of the second transistor with the voltage source based at least in part on the clock signal.

2. The apparatus of claim 1 , further comprising:
a third switching circuit configurable to couple the source node of the first transistor with the voltage source based at least in part on the clock signal and an enable signal.

3. The apparatus of claim 2 , wherein the third switching circuit comprises:
a third transistor and a fourth transistor in an electrically serial configuration between the source node of the first transistor and the voltage source, wherein the third transistor is configurable to be enabled based at least in part on the clock signal and the fourth transistor is configurable to be enabled based at least in part on the enable signal.

4. The apparatus of claim 2 , further comprising:
a fourth switching circuit configurable to couple the source node of the first transistor with the voltage source based at least in part on the clock signal and a second enable signal.

5. The apparatus of claim 2 , further comprising:
a fifth switching circuit configurable to couple the source node of the second transistor with the voltage source based at least in part on the clock signal and a third enable signal.

6. The apparatus of claim 5 , wherein the fifth switching circuit comprises:
a fifth transistor and a sixth transistor in an electrically serial configuration between the source node of the second transistor and the voltage source, wherein the fifth transistor is configurable to be enabled based at least in part on the clock signal and the sixth transistor is configurable to be enabled based at least in part on the third enable signal.

7. The apparatus of claim 6 , further comprising:
a sixth switching circuit configurable to couple the source node of the second transistor with the voltage source based at least in part on the clock signal and a fourth enable signal.

8. The apparatus of claim 2 , further comprising:
a register configured to store a configuration setting; and
circuitry configured to generate the enable signal based at least in part on the stored configuration setting.

9. The apparatus of claim 1 , wherein the voltage source is a ground voltage source.

10. The apparatus of claim 1 , wherein the circuitry configured to generate the output signal comprises:
circuitry configured to compare a voltage at the drain node of the first transistor to a voltage at the drain node of the second transistor.

11. The apparatus of claim 10 , wherein the circuitry configured to generate the output signal comprises:
a latch circuit configured to latch the output signal based at least in part on the comparison between the voltage at the drain node of the first transistor and the voltage at the drain node of the second transistor.

12. The apparatus of claim 11 , wherein the latch circuit is configured to latch the output signal based at least in part on the clock signal.

13. A method, comprising:
receiving, at a gate of a first transistor, a first input signal;
receiving, at a gate of a second transistor, a second input signal, wherein a source node of the second transistor is coupled with a source node of the first transistor via a resistor;
coupling, based at least in part on a clock signal and an enable signal, the source node of the first transistor with a ground voltage source via a switching circuit; and
generating, via circuitry coupled with a drain node of the first transistor and a drain node of the second transistor, an output signal based at least in part on the first input signal, the second input signal, and the coupling of the source node of the first transistor with the ground voltage source via the switching circuit.

14. The method of claim 13 , wherein coupling the source node of the first transistor with the ground voltage source comprises:
enabling a first transistor of the switching circuit based at least in part on biasing a gate of the first transistor of the switching circuit with the clock signal; and
enabling a second transistor of the switching circuit based at least in part on biasing a gate of the second transistor of the switching circuit with the enable signal.

15. The method of claim 13 , further comprising:
coupling, based at least in part on the clock signal and a second enable signal, the source node of the first transistor with the ground voltage source via a second switching circuit; and
generating the output signal based at least in part on the coupling of the source node of the first transistor with the ground voltage source via the second switching circuit.

16. The method of claim 13 , further comprising:
coupling, based at least in part on the clock signal and a third enable signal, the source node of the second transistor with the ground voltage source via a third switching circuit; and
generating the output signal based at least in part on the coupling of the source node of the second transistor with the ground voltage source via the third switching circuit.

17. The method of claim 13 , further comprising:
writing a configuration setting in a register circuit; and
generating the enable signal based at least in part on the configuration setting written at the register circuit.

18. The method of claim 17 , wherein writing the configuration setting comprises:
setting a state of a one-time programmable storage element.

19. The method of claim 13 , further comprising:
enabling one or more switching circuits of a plurality of switching circuits including the switching circuit, wherein each switching circuit of the plurality is configurable to couple the source node of the first transistor with the ground voltage source or to couple the source node of the second transistor with the ground voltage source;
evaluating an imbalance between the first transistor and the second transistor based at least in part on the enabling; and
generating the enable signal based at least in part on the evaluating.

20. The method of claim 13 , wherein generating the output signal comprises:
comparing a voltage of the drain node of the first transistor that is based at least in part on the first input signal to a voltage of the drain node of the second transistor that is based at least in part on the second input signal; and
latching a result of the comparing based at least in part on the clock signal.

21. A method, comprising:
receiving, at a gate of a first transistor of a memory device, a first signal from a host device;
receiving, at a gate of a second transistor of the memory device, a second signal, wherein a source of the second transistor is coupled with a source of the first transistor via a resistor;
connecting, based at least in part on a clock signal and an enable signal, the source o

Assignees

• Micron Technology Inc

Inventors

• Brox Martin
• Hein Thomas
• Balakrishnan Mani

Classifications

• G11C17/16

  using electrically-fusible links · CPC title

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title

• H03K5/249 Primary

  using clock signals · CPC title

• G11C27/02

  Sample-and-hold arrangements (G11C27/04 takes precedence) · CPC title

• G11C7/1087

  Data input latches · CPC title