Heterostructure of an electronic circuit having a semiconductor device

Patent metadata

Field	Value
Publication number	US-11699749-B2
Application number	US-201916509022-A
Country	US
Kind code	B2
Filing date	Jul 11, 2019
Priority date	Jul 12, 2018
Publication date	Jul 11, 2023
Grant date	Jul 11, 2023

Abstract

An electronic circuit having a semiconductor device is provided that includes a heterostructure, the heterostructure including a first layer of a compound semiconductor to which a second layer of a compound semiconductor adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), wherein the 2-dimensional electron gas is not present. In aspects, an electronic circuit having a semiconductor device is provided that includes a III-V heterostructure, the III-V heterostructure including a first layer including GaN to which a second layer adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), and having a purity such that the 2-dimensional electron gas is not present. It is therefore advantageous for the present electronic circuit to be enclosed such that, in operation, no light of wavelengths of less than 400 nm may reach the III-V heterostructure and free charge carriers may be generated by these wavelengths.

First claim

What is claimed is:

1. An electronic circuit having a semiconductor device that comprises:
a heterostructure including a first layer and a second layer that together form a channel,
wherein the heterostructure is a III-V heterostructure,
wherein the first layer includes fewer than 1×10 17 cm −3 oxygen atoms,
wherein the first layer comprises a compound semiconductor to which the second layer adjoins, and
wherein the channel, in the absence of an external field, is substantially free of electrons from a 2-dimensional electron gas.

2. The electronic circuit according to claim 1 , wherein the heterostructure includes GaN.

3. The electronic circuit according to claim 1 , wherein the heterostructure is formed from a ternary compound of a form Ga x K 1−x N with a trivalent element K, and wherein element K is aluminum or indium.

4. The electronic circuit according to claim 1 , wherein the second layer includes aluminum.

5. The electronic circuit according to claim 4 , wherein, in the second layer, the content of Ga is 94% and the content of Al is 6%.

6. The electronic circuit according to claim 1 , wherein the first layer includes fewer than 10 17 cm −3 free electrons that contribute to conductivity.

7. The electronic circuit according to claim 1 , wherein the second layer constitutes a barrier for charge carriers.

8. The electronic circuit according to claim 1 , wherein the 2-dimensional electron gas is generated using electromagnetic wave irradiation, in particular of a wavelength of less than 400 nm.

9. The electronic circuit according to claim 1 , wherein the 2-dimensional electron gas, at a positive electrical potential (normally-off), is formed between the channel and an interface of the second layer facing away from the channel.

10. The electronic circuit according to claim 1 , wherein an electrical potential is 1 V or higher.

11. The electronic circuit according to claim 1 , wherein the compound semiconductor layer has a purity, wherein the 2-dimensional electron gas is not present.

12. The electronic circuit according to claim 1 , wherein the first layer has a thickness of 100 nm or more.

13. The electronic circuit according to claim 1 , wherein the semiconductor device is implemented as a transistor.

14. The electronic circuit according to claim 13 , wherein two contacts and an isolating layer are implemented adjoining to the second semiconducting layer, such that the isolating layer partially extends across one of the two contacts.

15. The electronic circuit according to claim 14 , wherein a further contact is implemented adjoining to the isolating layer, the contact partially extending across one of the two contacts, separated by the isolating layer.

16. An electronic circuit having a semiconductor device that comprises:
a heterostructure including a first layer and a second layer that together form a channel,
wherein the first layer has a dislocation defect density of less than 10 7 cm −2 ,
wherein the first layer comprises a compound semiconductor to which the second layer adjoins, and
wherein the channel, in the absence of an external field, is substantially free of electrons from a 2-dimensional electron gas.

17. The electronic circuit according to claim 16 , wherein the heterostructure is a III-V heterostructure.

18. The electronic circuit according to claim 16 , wherein the heterostructure is a II-VI heterostructure.

19. The electronic circuit according to claim 18 , wherein the heterostructure includes ZnO.

Assignees

• Namlab Ggmbh
• Univ Dresden Tech

Inventors

• Schmult Stefan
• Wachowiak Andre
• Ruf Alexander

Classifications

• H01L29/7787 Primary

  Electricity · mapped topic

• H01L29/205

  Electricity · mapped topic

• H01L29/7788

  Electricity · mapped topic

• H01L29/2003

  Electricity · mapped topic

• H01L29/225

  Electricity · mapped topic