Quantum dot devices with multiple layers of gate metal

Patent metadata

Field	Value
Publication number	US-11699747-B2
Application number	US-201916365018-A
Country	US
Kind code	B2
Filing date	Mar 26, 2019
Priority date	Mar 26, 2019
Publication date	Jul 11, 2023
Grant date	Jul 11, 2023

Abstract

Disclosed herein are quantum dot devices with multiple layers of gate metal, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; an insulating material above the quantum well stack, wherein the insulating material includes a trench; and a gate on the insulating material and extending into the trench, wherein the gate includes a first gate metal in the trench and a second gate metal above the first gate metal.

First claim

The invention claimed is:

1. A quantum dot device, comprising:
a quantum well stack;
an insulating material above the quantum well stack, wherein the insulating material includes a trench; and
a gate, wherein the gate includes a first gate metal in the trench and a second gate metal above the first gate metal,
wherein at least one of:
the first gate metal and the second gate metal have different material compositions,
the first gate metal and the second gate metal have different microstructures, or
a seam is present between the first gate metal and the second gate metal.

2. The quantum dot device of claim 1 , wherein the trench is a first trench, the gate is a first gate, the insulating material further includes a second trench, and the quantum dot device further comprises:
a second gate on the insulating material and extending into the second trench, wherein the second gate includes a third gate metal in the second trench and a fourth gate metal above the third gate metal.

3. The quantum dot device of claim 1 , wherein the trench has a tapered profile that is narrowest proximate to the quantum well stack.

4. The quantum dot device of claim 1 , wherein the trench extends down to the quantum well stack.

5. The quantum dot device of claim 1 , wherein the gate is a first gate, and the quantum dot device further comprises:
a second gate on the insulating material and extending into the trench, wherein the second gate is electrically insulated from the first gate.

6. The quantum dot device of claim 5 , further comprising:
at least one spacer between the first gate and the second gate.

7. The quantum dot device of claim 6 , wherein the at least one spacer between the first gate and the second gate includes a stack of two spacers.

8. The quantum dot device of claim 7 , wherein a bottom spacer in the stack of two spacers is in the trench and a top spacer in the stack of two spacers is above the trench.

9. The quantum dot device of claim 5 , wherein the second gate includes a third gate metal in the trench and a fourth gate metal above the third gate metal.

10. The quantum dot device of claim 5 , wherein the second gate includes a third gate metal in the trench and extending above the trench.

11. The quantum dot device of claim 1 , wherein the first gate metal includes columnar grains.

12. A method of manufacturing a quantum dot device, the method comprising:
forming a quantum well stack;
forming an insulating material above the quantum well stack, wherein the insulating material includes a trench; and
forming a gate, wherein the gate includes a first gate metal in the trench and a second gate metal above the first gate metal,
wherein at least one of:
the first gate metal and the second gate metal have different material compositions,
the first gate metal and the second gate metal have different microstructures, or
a seam is present between the first gate metal and the second gate metal.

13. The method of claim 12 , wherein forming the insulating material above the quantum well stack includes:
depositing the insulating material above the quantum well stack; and
removing at least some of the insulating material to form the trench.

14. The method of claim 12 , wherein forming the insulating material above the quantum well stack includes:
depositing the insulating material over the first gate metal; and
polishing back the insulating material.

15. A quantum computing device, comprising:
a quantum processing device, wherein the quantum processing device includes an insulating material having a trench that extends toward a quantum well layer, and a plurality of gates, wherein a gate of the plurality of gates includes a first layer of gate metal and a second layer of gate metal, wherein the first layer of gate metal is between the second layer of gate metal and the quantum well layer, the first layer of gate metal is in the trench, and the first layer of gate metal has a different microstructure than the second layer of gate metal;
a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to the plurality of gates of the quantum processing device; and
a memory device to store data generated by quantum dots formed in the quantum well layer during operation of the quantum processing device.

16. The quantum computing device of claim 15 , wherein the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device.

17. The quantum computing device of claim 15 , wherein the first layer of gate metal and the second layer of gate metal have different material compositions.

18. The quantum computing device of claim 15 , wherein the first layer of gate metal and the second layer of gate metal have a same material composition.

19. The quantum computing device of claim 15 , wherein the quantum processing device includes a seam between the first layer of gate metal and the second layer of gate metal.

Assignees

• Intel Corp

Inventors

• George Hubert C
• Atanasov Sarah
• Pillarisetty Ravi
• Lampert Lester
• Clarke James S
• Thomas Nicole K
• Caudillo Roman
• Singh Kanwaljit
• Michalak David J
• Roberts Jeanette M
• Bojarski Stephanie A

Classifications

• H01L29/4236

  Electricity · mapped topic

• H10D30/014

  of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors · CPC title

• H01L29/7613

  Electricity · mapped topic

• G06N10/00

  Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title

• B82Y10/00 Primary

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title