Semiconductor device with metal interconnection

Patent metadata

Field	Value
Publication number	US-11699658-B2
Application number	US-202016889467-A
Country	US
Kind code	B2
Filing date	Jun 1, 2020
Priority date	Dec 30, 2019
Publication date	Jul 11, 2023
Grant date	Jul 11, 2023

Abstract

A semiconductor device includes: a substrate; a test transistor over the substrate; and multi-level metal interconnections formed over the substrate spaced apart from the test transistor, wherein at least one metal interconnection among the multi-level metal interconnections is a spiral metal interconnection.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a test transistor over the substrate; and
multi-level metal interconnections formed over the substrate and spaced apart from each other and from the test transistor in a vertical direction from the substrate; and
contacts for connecting the metal interconnections,
wherein at least one metal interconnection among the multi-level metal interconnections is a spiral metal interconnection, and
wherein the contacts do not overlap with each other,
wherein at least the lowest-level metal interconnection among the multi-level metal interconnections is a spiral metal interconnection.

2. The semiconductor device of claim 1 , wherein the spiral metal interconnection has a current flow that offsets plasma-induced damage occurring from other metal interconnections among the multi-level metal interconnections.

3. The semiconductor device of claim 1 ,
wherein an upward contact of each metal interconnection is coupled to a first end of each metal interconnection, and
a downward contact of each metal interconnection is coupled to a second end of each metal interconnection.

4. The semiconductor device of claim 3 , wherein the upward contact and the downward contact do not overlap with each other.

5. The semiconductor device of claim 1 , wherein the multi-level metal interconnections are spiral metal interconnections.

6. The semiconductor device of claim 1 , wherein a spiral structure of the at least one metal interconnection has a round shape or a bend shape.

7. The semiconductor device of claim 6 , wherein the round shape includes a circular shape or an elliptical shape, and
wherein the bend shape includes one shape selected from among polygonal structures including a rectangle, a square, and an octagon.

8. The semiconductor device of claim 1 , wherein the multi-level metal interconnections are positioned at a higher level than the test transistor.

9. The semiconductor device of claim 1 , wherein the test transistor includes a gate structure over the substrate, and source/drain regions formed in the substrate on both sides of the gate structure, and
wherein the multi-level metal interconnections are coupled to one of the source/drain regions.

10. A semiconductor device, comprising:
a substrate including a cell region and a peripheral region;
an inter-layer dielectric layer formed over the substrate;
a capacitor formed over the inter-layer dielectric layer in the cell region and including a stacked structure of a lower electrode, a dielectric layer, and an upper electrode;
a storage node contact penetrating the inter-layer dielectric layer and connecting the capacitor and the substrate in the cell region;
multi-level cell metal interconnections formed over the capacitor of the cell region, and multi-level peripheral metal interconnections formed over the substrate of the peripheral region; and
a cell pad formed over the multi-level cell metal interconnections, and a peripheral pad formed over the multi-level peripheral metal interconnections,
wherein at least one metal interconnection among the multi-level cell metal interconnections and the peripheral metal interconnections is a spiral metal interconnection.

11. The semiconductor device of claim 10 , wherein at least one lowest-level metal interconnection among the multi-level cell metal interconnections and the multi-level peripheral metal interconnections is a spiral metal interconnection.

12. The semiconductor device of claim 10 , wherein the multi-level cell metal interconnections and the multi-level peripheral metal interconnections are spiral metal interconnections.

13. The semiconductor device of claim 10 , wherein the spiral structure has a round shape or a bend shape.

14. The semiconductor device of claim 13 , wherein the round shape includes a circular shape or an elliptical shape, and
wherein the bend shape includes one shape selected from among polygonal structures including a rectangle, a square, and an octagon.

Assignees

• Sk Hynix Inc

Inventors

• Lee Eunsung

Classifications

• H01L22/34

  Electricity · mapped topic

• H01L23/5283 Primary

  Electricity · mapped topic

• H01L23/5226

  Electricity · mapped topic

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title