Anti-fuse memory circuit

Patent metadata

Field	Value
Publication number	US-11699496-B2
Application number	US-202217674882-A
Country	US
Kind code	B2
Filing date	Feb 18, 2022
Priority date	Jul 8, 2021
Publication date	Jul 11, 2023
Grant date	Jul 11, 2023

Abstract

An anti-fuse memory circuit includes: a memory array including multiple anti-fuse memory cells; bit lines, each connected to the anti-fuse memory cells arranged in extension direction of the bit line, each anti-fuse memory cell being electrically connected to respective one of bit lines through first switch transistor; word lines, each connected to first switch transistors arranged in extension direction of word line; a second switch transistor connects one of the bit lines to transmission wire; a reading circuit, having first input terminal connected to the transmission wire, second input terminal for receiving reference voltage, and sampling input terminal for receiving sampling signal; and a signal generation circuit for generating sampling signal according to precharge voltage and precharge signal, where precharge signal is used for instructing to precharge transmission wire to precharge voltage, and delay duration between sampling signal and precharge signal is positively correlated with voltage amplitude of precharge voltage.

First claim

The invention claimed is:

1. An anti-fuse memory circuit, comprising:
a memory array, comprising a plurality of anti-fuse memory cells, the anti-fuse memory cell representing stored 1-bit data by whether a gate oxide layer is broken down;
bit lines, each of which is connected to the anti-fuse memory cells arranged in an extension direction of the bit line, each anti-fuse memory cell being electrically connected to a respective one of the bit lines through a first switch transistor;
word lines, each of which is connected to the first switch transistors arranged in an extension direction of the word line and configured to turn on a selected first switch transistor according to a row strobe signal, wherein the extension direction of the bit line and the extension direction of the word line are perpendicular to each other;
a second switch transistor, configured to connect one of the bit lines to a transmission wire;
a reading circuit, comprising a first input terminal, a second input terminal and a sampling input terminal, wherein the first input terminal is connected to the transmission wire, the second input terminal is configured to receive a reference voltage, and the sampling input terminal is configured to receive a sampling signal; and
a signal generation circuit, configured to generate the sampling signal according to a precharge voltage and a precharge signal, wherein the precharge signal is used for instructing to precharge the transmission wire to the precharge voltage, and a delay duration between the sampling signal and the precharge signal is positively correlated with a voltage amplitude of the precharge voltage,
wherein when the sampling signal is a valid pulse, the reading circuit compares an input voltage of the first input terminal with the reference voltage, to output the 1-bit data stored in the anti-fuse memory cell.

2. The anti-fuse memory circuit of claim 1 , wherein the reading circuit comprises:
a comparator, comprising the first input terminal, the second input terminal, and an output terminal; and
a latch device, comprising the sampling input terminal and a data input terminal, wherein the data input terminal is connected to the output terminal of the comparator,
wherein the comparator is configured to compare the input voltage of the first input terminal with the reference voltage, and the latch device is configured to output the 1-bit data stored in the anti-fuse memory cell.

3. The anti-fuse memory circuit of claim 2 , wherein the signal generation circuit comprises:
a signal delay sub-circuit, configured to: receive the precharge signal, and delay the precharge signal to output a charging delay signal; and
a pulse conversion sub-circuit, configured to: receive the charging delay signal, generate a pulse signal based on the charging delay signal, and input the pulse signal into the sampling input terminal as the sampling signal.

4. The anti-fuse memory circuit of claim 3 , wherein the signal delay sub-circuit comprises a first current mirror, a second current mirror, a first Metal-Oxide-Semiconductor (MOS) inverter, and a second MOS inverter,
wherein a first terminal of the first current mirror is connected to the precharge voltage through an input resistor, and a second terminal of the first current mirror is connected to a first terminal of the second current mirror;
the first terminal of the second current mirror is connected to the precharge voltage through a constant current source, and a second terminal of the second current mirror outputs a drive current of the first MOS inverter;
an input terminal of the first MOS inverter is configured to receive the precharge signal, and an output terminal of the first MOS inverter is connected to an input terminal of the second MOS inverter; and
an output terminal of the second MOS inverter is configured to output the charging delay signal.

5. The anti-fuse memory circuit of claim 4 , wherein:
the first MOS inverter comprises a first Negative-channel MOS (NMOS) transistor and a first Positive-channel MOS (PMOS) transistor, a drain of the first NMOS transistor being connected to a drain of the first PMOS transistor, wherein a gate of the first NMOS transistor and a gate of the first PMOS transistor are configured to receive the precharge signal, a source of the first PMOS transistor is configured to receive the precharge voltage, and a source of the first NMOS transistor is configured to receive the drive current outputted by the second current mirror; and
the second MOS inverter comprises a second NMOS transistor and a second PMOS transistor, a drain of the second NMOS transistor being connected to a drain of the second PMOS transistor, wherein a gate of the second NMOS transistor and a gate of the second PMOS transistor are connected to the drain of the first NMOS transistor, a source of the second PMOS transistor is configured to receive the precharge voltage, and a source of the second NMOS transistor is grounded.

6. The anti-fuse memory circuit of claim 3 , wherein the pulse conversion sub-circuit comprises:
an inverter circuit, comprising an odd number of stages of inverters connected in series, and having an input terminal configured to receive the charging delay signal; and
an AND gate, having an input terminal connected to an output terminal of the inverter circuit and another input terminal configured to receive the charging delay signal, and configured to generate the pulse signal according to the charging delay signal and the charging delay signal that is delayed by the inverter circuit.

7. The anti-fuse memory circuit of claim 6 , wherein the odd number of stages of inverters connected in series are three inverters connected in series.

8. The anti-fuse memory circuit of claim 1 , further comprising: a voltage adjustment circuit comprising a voltage division circuit having a plurality of resistors connected in series, one terminal of the voltage division circuit being configured to receive the precharge voltage, and the other terminal of the voltage division circuit being grounded, and the voltage division circuit being configured to generate the reference voltage by dividing the precharge voltage, and input the reference voltage to the second input terminal.

9. The anti-fuse memory circuit of claim 8 , wherein the reference voltage is 60%-80% of the precharge voltage.

10. The anti-fuse memory circuit of claim 1 , wherein a gate of the first switch transistor is connected to the word line, one of a source or a drain of the first switch transistor is connected to the anti-fuse memory cell, and the other one of the source or drain is connected to the bit line.

11. The anti-fuse memory circuit of claim 10 , wherein in the extension direction of the bit line, every two first switch transistors are connected to the bit line through a same conductive wire.

12. The anti-fuse memory circuit of claim 1 , wherein a gate of the second switch transistor is configured to receive a column strobe signal, one of a source or a drain of the second switch transistor is connected to the bit line, and the other one of the source or drain is connected to the transmission wire, wherein the column strobe signal is used for selecting one of the bit lines and turning on one second switch transistor connected to a selected bit line.

13. The anti-fuse memory circuit of claim 1 , further comprising a precharge MOS transistor having one of a source or a drain configured to receive the precharge voltage, the other one of the source or the drain connected to the transmission wire, and a gate configured to receive the precharge signal; wherein the precharge MOS transistor is configured to prec

Assignees

• Changxin Memory Tech Inc

Inventors

• Ji Rumin

Classifications

• G11C17/16 Primary

  using electrically-fusible links · CPC title

• G11C17/18 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title