Non-volatile memory device, operating method thereof, controller for controlling the same, and storage device including the same

Patent metadata

Field	Value
Publication number	US-11699490-B2
Application number	US-202117220218-A
Country	US
Kind code	B2
Filing date	Apr 1, 2021
Priority date	Aug 14, 2020
Publication date	Jul 11, 2023
Grant date	Jul 11, 2023

Abstract

An operating method of a storage device includes reading a wear-out pattern of a memory block when a controller determines the memory block is a re-use memory block of a non-volatile memory device; selecting an operation mode corresponding to the read wear-out pattern using the controller; and transmitting the selected operation mode to the non-volatile memory device using the controller.

First claim

What is claimed is:

1. An operating method of a storage device, the method comprising:
reading a wear-out pattern of a memory block when a controller determines the memory block is a re-use memory block of a non-volatile memory device;
selecting an operation mode corresponding to the wear-out pattern using the controller; and
transmitting the operation mode to the non-volatile memory device using the controller.

2. The method of claim 1 , wherein the wear-out pattern is stored in a meta region of the non-volatile memory device or in the memory block of the non-volatile memory device.

3. The method of claim 1 , wherein the wear-out pattern includes information on charge loss or charge gain of the memory block.

4. The method of claim 1 , wherein the selected operation mode includes an advanced operation mode for improving reliability.

5. The method of claim 4 , wherein, in a program operation, a read operation, or an erase operation, the advanced operation mode varies a word-line recovery level, differently from a normal operation mode, according to the wear-out pattern.

6. The method of claim 1 , wherein the non-volatile memory device includes a memory cell region and a peripheral circuit region,
the memory cell region has a first metal pad, and
the peripheral circuit region has a second metal pad and is vertically connected to the first metal pad through the second metal pad, and
the first metal pad is connected to the second metal pad by a bonding method.

7. The method of claim 6 ,
wherein the memory cell region is on a first wafer, and
wherein the peripheral circuit region is on a second wafer different from the first wafer.

8. The method of claim 6 , wherein
an extension direction of a first plug corresponding to the first metal pad and an extension direction of a second plug corresponding to the second metal pad are opposite to each other.

9. An operating method of a storage device, the method comprising:
reading a wear-out pattern of a memory block when a controller determines the memory block is a re-use memory block of a non-volatile memory device;
selecting an operation mode corresponding to the wear-out pattern using the controller; and
transmitting the operation mode to the non-volatile memory device using the controller;
performing a patrol read operation for the memory block before the memory block is reused; and
determining whether a reclaim is necessary as a result of the patrol read operation.

10. The method of claim 9 , further comprising:
performing the reclaim for the memory block when the reclaim is necessary for the memory block; and
storing the wear-out pattern corresponding to the memory block.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Gwak Soyeong
• Lee Raeyoung
• Kang Jinkyu
• Park Sejun
• Shin Changhwan
• Lee Jaeduk
• Jang Woojae

Classifications

• G11C7/1087

  Data input latches · CPC title

• G11C16/16 Primary

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/349 Primary

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G11C7/106

  Data output latches · CPC title