Display panel having optical component region and display device

US11699389B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11699389-B2
Application numberUS-202217709801-A
CountryUS
Kind codeB2
Filing dateMar 31, 2022
Priority dateJul 28, 2020
Publication dateJul 11, 2023
Grant dateJul 11, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display panel and a display device are provided in the present disclosure. The display panel includes a plurality of pixels, including first pixels and second pixels, where each of the first pixels includes a first light-emitting element connected with a first pixel circuit; the first pixel circuit includes a first drive transistor; each of the second pixels includes a second light-emitting element connected with a second pixel circuit; and the second pixel circuit includes a second drive transistor. The display panel further includes a display region, including an optical component region and a first display region, where the first light-emitting element is in the optical component region; the second light-emitting element is in the first display region.

First claim

Opening claim text (preview).

What is claimed is: 1. A display panel, comprising: a plurality of pixels, including first pixels and second pixels, wherein each of the first pixels includes a first light-emitting element connected with a first pixel circuit; the first pixel circuit includes a first drive transistor; each of the second pixels includes a second light-emitting element connected with a second pixel circuit; and the second pixel circuit includes a second drive transistor; and a display region, including an optical component region and a first display region, wherein the first light-emitting element is in the optical component region; and the second light-emitting element is in the first display region, wherein: the first pixels include first blue pixels, first red pixels, and first green pixels; a width-to-length ratio of a first drive transistor corresponding to a first blue pixel is R1, a width-to-length ratio of a first drive transistor corresponding to a first red pixel is R2, and a width-to-length ratio of a first drive transistor corresponding to a first green pixel is R3, the second pixels include second blue pixels, second red pixels, and second green pixels; a width-to-length ratio of a second drive transistor corresponding to a second blue pixel is R1′, a width-to-length ratio of a second drive transistor corresponding to a second red pixel is R2′, and a width-to-length ratio of a second drive transistor corresponding to a second green pixel is R3′, wherein R1>R1′, R2>R2′, and/or R3>R3′, and the first pixel circuit includes a first storage capacitor electrically connected to a gate electrode of the first drive transistor; the second pixel circuit includes a second storage capacitor electrically connected to a gate electrode of the second drive transistor; and a capacitance of the first storage capacitor is greater than a capacitance of the second storage capacitor. 2. The display panel according to claim 1 , wherein: a channel width of the first drive transistor corresponding to the first red pixel is W2, a channel width of the first drive transistor corresponding to the first green pixel is W3, a channel length of the first drive transistor corresponding to the first red pixel is L2, and a channel length of the first drive transistor corresponding to the first green pixel is L3, wherein |W2−W3|0.5 μm, and |L2−L3|0.5 μm. 3. The display panel according to claim 1 , wherein: the first pixel circuit includes a reset module, a data write module, and a light-emitting control module which are electrically connected to the first drive transistor; the reset module includes at least one reset transistor electrically connected to the first drive transistor; the data write module includes at least one data write transistor electrically connected to the first drive transistor; and the light-emitting control module includes at least one light-emitting control transistor electrically connected to the first drive transistor; and a width-to-length ratio of a light-emitting control transistor corresponding to the first pixel circuit is greater than each of width-to-length ratios of the reset transistor and the data write transistor in a same first pixel circuit. 4. The display panel according to claim 3 , wherein: the first pixel circuit further includes a black state maintaining module electrically connected to the first light-emitting element, and the black state maintaining module includes at least one black state maintaining transistor electrically connected to the first light-emitting element; and the width-to-length ratio of the light-emitting control transistor corresponding to the first pixel circuit is greater than a width-to-length ratio of the black state maintaining transistor in a same first pixel circuit. 5. The display panel according to claim 3 , wherein: the width-to-length ratio of the light-emitting control transistor corresponding to the first pixel circuit is R k , wherein 4≤R k ≤6. 6. The display panel according to claim 1 , wherein: the capacitance of the first storage capacitor is C1, and the capacitance of the second storage capacitor is C2, wherein 2≤C1/C2≤4. 7. The display panel according to claim 1 , wherein: in the first drive transistor corresponding to the first blue pixel, the first drive transistor corresponding to the first red pixel, the first drive transistor corresponding to the first green pixel, at least the first drive transistor corresponding to the first blue pixel has a channel in a rectangular shape. 8. A display device with the display panel according to claim 1 . 9. A display panel, comprising: a plurality of pixels, including first pixels and second pixels, wherein each of the first pixels includes a first light-emitting element connected with a first pixel circuit; the first pixel circuit includes a first drive transistor; each of the second pixels includes a second light-emitting element connected with a second pixel circuit; and the second pixel circuit includes a second drive transistor; and a display region, including an optical component region and a first display region, wherein the first light-emitting element is in the optical component region; and the second light-emitting element is in the first display region, wherein: the first pixels include first blue pixels, first red pixels, and first green pixels; a width-to-length ratio of a first drive transistor corresponding to a first blue pixel is R1, a width-to-length ratio of a first drive transistor corresponding to a first red pixel is R2, and a width-to-length ratio of a first drive transistor corresponding to a first green pixel is R3, the second pixels include second blue pixels, second red pixels, and second green pixels; a width-to-length ratio of a second drive transistor corresponding to a second blue pixel is R1′, a width-to-length ratio of a second drive transistor corresponding to a second red pixel is R2′, and a width-to-length ratio of a second drive transistor corresponding to a second green pixel is R3′, wherein R1>R1′, R2>R2′, and/or R3>R3′, and among the first drive transistor corresponding to the first blue pixel, the first drive transistor corresponding to the first red pixel, and the first drive transistor corresponding to the first red pixel, at least the first drive transistor corresponding to the first blue pixel has a rectangular shaped channel. 10. The display panel according to claim 9 , wherein: a channel width of the first drive transistor corresponding to the first red pixel is W2, a channel width of the first drive transistor corresponding to the first green pixel is W3, a channel length of the first drive transistor corresponding to the first red pixel is L2, and a channel length of the first drive transistor corresponding to the first green pixel is L3, wherein |W2−W3|≤0.5 μm, and |L2−L3|≤0.5 μm. 11. The display panel according to claim 9 , wherein: the first pixel circuit includes a reset module, a data write module, and a light-emitting control module which are electrically connected to the first drive transistor; the reset module includes at least one reset transistor electrically connected to the first drive transistor; the data write module includes at least one data write transistor electrically connected to the first drive transistor; and the light-emitting control module includes at least one light-emitting control transistor electrically connected to the first drive transistor; and a width-to-length ratio of a light-emitting control transistor corresponding to the first pixel circuit is greater than each of width-to-length ratios of the reset transistor and the data write transistor in a same first pixel circuit. 12. The display panel

Assignees

Inventors

Classifications

  • Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters · CPC title

  • G09G3/32Primary

    semiconductive, e.g. using light-emitting diodes [LED] · CPC title

  • Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components · CPC title

  • Display of colours (specific for liquid crystal displays G09G3/3607) · CPC title

  • H10K59/12Primary

    Active-matrix OLED [AMOLED] displays · CPC title

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What does patent US11699389B2 cover?
A display panel and a display device are provided in the present disclosure. The display panel includes a plurality of pixels, including first pixels and second pixels, where each of the first pixels includes a first light-emitting element connected with a first pixel circuit; the first pixel circuit includes a first drive transistor; each of the second pixels includes a second light-emitting e…
Who is the assignee on this patent?
Wuhan Tianma Micro Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/32. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 11 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).