System, device and method for generating a biasing current

Patent metadata

Field	Value
Publication number	US-11698653-B2
Application number	US-201916520112-A
Country	US
Kind code	B2
Filing date	Jul 23, 2019
Priority date	Jul 23, 2019
Publication date	Jul 11, 2023
Grant date	Jul 11, 2023

Abstract

Various implementations described herein are directed to multi-stage system. The system may include a first stage having a current bias generator that generates a biasing current. The system may include a second stage that is coupled to the first stage, and the second stage may include a load that utilizes the biasing current generated by the current bias generator.

First claim

What is claimed is:

1. A system, comprising:
a first stage having a current bias generator that generates a biasing current, the current bias generator including a resistor structure that comprises an emulated resistor;
a second stage coupled to the first stage, wherein the second stage has a load that utilizes the biasing current generated by the current bias generator; and
a reference voltage generator that generates a reference voltage,
wherein the reference voltage generator includes a first native device structure and a first plurality of stacking transistor structures that are coupled in series between the supply voltage and ground,
wherein the first native device structure includes a gate that is coupled between a first transistor and a second transistor of the first plurality of stacking transistor structures,
wherein the resistor structure has a second plurality of stacking transistor structures coupled in series, and
wherein the reference voltage is used to activate the second plurality of stacking transistor structures.

2. The system of claim 1 , wherein the current bias generator has a native device structure with a gate coupled to ground.

3. The system of claim 2 , wherein the resistor structure of the current bias generator is coupled between a source terminal of the native device structure and ground.

4. A system, comprising:
a first stage having a current bias generator that generates a biasing current, the current bias generator including a resistor structure that comprises an emulated resistor;
a second stage coupled to the first stage, wherein the second stage has a load that utilizes the biasing current generated by the current bias generator; and
a reference voltage generator that generates a reference voltage,
wherein the reference voltage generator includes a first native device structure and a first plurality of stacking transistor structures that are coupled in series between the supply voltage and ground,
wherein the first native device structure includes a gate that is coupled between a first transistor and a second transistor of the first plurality of stacking transistor structures,
wherein the resistor structure has a second plurality of stacking transistor structures coupled in series,
wherein the current bias generator has a native device structure with a gate coupled to ground,
wherein the resistor structure of the current bias generator is coupled between a source terminal of the native device structure and ground, and
wherein the reference voltage is used to activate the second plurality of stacking transistor structures.

5. The system of claim 1 , wherein:
the second stage is coupled in parallel with the first stage,
the first stage has a first stacking transistor structure coupled between a supply voltage and the current bias generator, and
the current bias generator is coupled between the first stacking transistor structure and ground.

6. The system of claim 5 , wherein the first stacking transistor structure is coupled as a diode.

7. The system of claim 5 , wherein the second stage has a second stacking transistor structure coupled between the supply voltage and the load, and wherein the load is coupled between the second stacking transistor structure and ground.

8. The system of claim 7 , wherein a gate of the first stacking transistor structure is coupled to a gate of the second stacking transistor structure.

9. The system of claim 1 , wherein:
the second stage is coupled in series with the first stage,
the first stage is coupled between the second stage and ground, and
the second stage is coupled between a supply voltage and the first stage.

10. A device, comprising:
a first native device structure that is configured to receive a supply voltage, wherein the first native device structure has a gate coupled to ground;
a resistor structure comprising an emulated resistor coupled between the native device structure and ground, wherein the first native device structure and the resistor structure are configured to generate a biasing current for a load; and
a reference voltage generator that generates a reference voltage,
wherein the reference voltage generator includes a second native device structure and a first plurality of stacking transistor structures that are coupled in series between the supply voltage and ground,
wherein the second native device structure includes a gate that is coupled between a first transistor and a second transistor of the first plurality of stacking transistor structures,
wherein the resistor structure has a second plurality of stacking transistor structures coupled in series, and
wherein the reference voltage is used to activate the first plurality of stacking transistor structures.

11. The device of claim 10 , wherein the load is coupled in parallel with the native device structure and the resistor structure.

12. The device of claim 10 , wherein the load is coupled in series with the native device structure and the resistor structure.

13. A method, comprising:
coupling a gate of a first native device structure to ground;
coupling a resistor structure between the first native device structure and ground, the resistor structure comprising an emulated resistor;
coupling a load to the first native device structure;
generating a biasing current for the load with the first native device structure and the resistor structure; and
generating a reference voltage with a reference voltage generator,
wherein the reference voltage generator includes a second native device structure and a first plurality of stacking transistor structures that are coupled in series between a supply voltage and ground,
wherein the second native device structure includes a gate that is coupled between a first transistor and a second transistor of the first plurality of stacking transistor structures,
wherein the resistor structure has a second plurality of stacking transistor structures coupled in series, and
wherein the reference voltage is used to activate the second plurality of stacking transistor structures.

14. The method of claim 13 , wherein the resistor structure is coupled between a source terminal of the native device structure and ground.

15. A method, comprising:
coupling a gate of a first native device structure to ground;
coupling a resistor structure between the first native device structure and ground, the resistor structure comprising an emulated resistor;
coupling a load to the first native device structure;
generating a biasing current for the load with the first native device structure and the resistor structure; and
generating a reference voltage with a reference voltage generator,
wherein the reference voltage generator includes a second native device structure and a first plurality of stacking transistor structures that are coupled in series between a supply voltage and ground,
wherein the second native device structure includes a gate that is coupled between a first transistor and a second transistor of the first plurality of stacking transistor structures,
wherein the resistor structure has a second plurality of stacking transistor structures coupled in series,
wherein the resistor structure is coupled between a source terminal of the native device structure and ground, and
wherein the reference voltage is used to activate the second plurality of stacking transistor structures.

16. The system of claim 4 , wherein the stacking transistor structures operate in a triode region and behave as resistors.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Fan Philex Ming-Yan
• Labbe Benoit
• Savanth Parameshwarappa Anand Kumar

Classifications

• H03L1/00

  Stabilisation of generator output against variations of physical values, e.g. power supply · CPC title

• G05F3/20 Primary

  using diode- transistor combinations (G05F3/18 takes precedence) · CPC title

• G05F3/24 Primary

  wherein the transistors are of the field-effect type only (G05F3/205, G05F3/26, G05F3/30 take precedence) · CPC title

• G05F3/262

  using field-effect transistors only · CPC title