Automatic read calibration operations

Patent metadata

Field	Value
Publication number	US-11693582-B2
Application number	US-202016947592-A
Country	US
Kind code	B2
Filing date	Aug 7, 2020
Priority date	Aug 7, 2020
Publication date	Jul 4, 2023
Grant date	Jul 4, 2023

Abstract

An apparatus comprises a plurality of memory cells; a plurality of sense circuits, a sense circuit comprising a sense node selectively coupled to a bitline coupled to a first cell of the plurality of memory cells; and a controller to transpose a value indicative of a voltage of the first cell to the sense node; isolate the sense node from the bitline; and calibrate a parameter for the sense circuit based on outputs of the sense circuit for each of a plurality of different applied values of the parameter.

First claim

What is claimed is:

1. An apparatus comprising:
a plurality of memory cells;
a plurality of sense circuits, a sense circuit comprising a sense node selectively coupled to a bitline coupled to a first cell of the plurality of memory cells; and
a controller to:
transpose a value indicative of a voltage of the first cell to the sense node;
isolate the sense node from the bitline;
calibrate a parameter for the sense circuit based on outputs of the sense circuit for each of a plurality of different applied values of the parameter; and
store the calibrated parameter and apply the calibrated parameter in a subsequent read operation.

2. The apparatus of claim 1 , wherein the parameter comprises a boost node voltage coupled through a capacitor to the sense node.

3. The apparatus of claim 1 , wherein the parameter comprises a reference voltage coupled to a sense amplifier of the sense circuit.

4. The apparatus of claim 1 , wherein calibrating the parameter comprises determining an interpolated value in between two of the applied values of the parameter.

5. The apparatus of claim 4 , wherein calibrating the parameter comprises determining the interpolated value based on a histogram comprising a count of number of bits that flipped between a first page read when a first value is applied for the parameter and a second page read when a second value is applied for the parameter.

6. The apparatus of claim 5 , wherein calibrating the parameter comprises shifting the count and comparing the shifted count to a second count of a second histogram.

7. The apparatus of claim 6 , wherein calibrating the parameter comprises adjusting a variable representing the parameter by a step voltage based on the comparison.

8. The apparatus of claim 1 , further comprising a memory to store a calibration enable parameter, wherein the controller is configured to calibrate the parameter when a read is performed if the calibration enable parameter is set and to perform a regular read operation if the calibration enable parameter is not set.

9. The apparatus of claim 8 , wherein the controller is to receive a request to set the calibration enable parameter from a host computing device.

10. The apparatus of claim 1 , wherein the controller is to receive at least one of the applied values of the parameter from a host computing device.

11. A method comprising:
transposing a value indicative of a voltage of a first memory cell to a sense node of a sense circuit;
isolating the sense node from a bitline selectively coupled to the first memory cell;
calibrating a parameter for the sense circuit based on outputs of the sense circuit for each of a plurality of different applied values of the parameter; and
storing, by a controller, the calibrated parameter and applying, by the controller, the calibrated parameter in a subsequent read operation.

12. The method of claim 11 , wherein the parameter comprises a boost node voltage coupled through a capacitor to the sense node.

13. The method of claim 11 , wherein the parameter comprises a reference voltage coupled to a sense amplifier of the sense circuit.

14. The method of claim 11 , wherein calibrating the parameter comprises determining an interpolated value in between two of the applied values of the parameter.

15. The method of claim 14 , wherein calibrating the parameter comprises determining the interpolated value based on a histogram comprising a count of number of bits that flipped between a first page read when a first value is applied for the parameter and a second page read when a second value is applied for the parameter.

16. A storage device comprising:
a storage device controller; and
a plurality of memory chips, wherein a memory chip comprises:
a plurality of memory cells;
a plurality of sense circuits, a sense circuit comprising a sense node selectively coupled to a bitline coupled to a first cell of the plurality of memory cells; and
a memory chip controller to:
transpose a value indicative of a voltage of the first cell to the sense node;
isolate the sense node from the bitline;
calibrate a parameter for the sense circuit based on outputs of the sense circuit for each of a plurality of different applied values of the parameter; and
store the calibrated parameter and apply the calibrated parameter in a subsequent read operation.

17. The storage device of claim 16 , wherein the parameter comprises a boost node voltage coupled through a capacitor to the sense node.

18. The storage device of claim 16 , wherein the parameter comprises a reference voltage coupled to a sense amplifier of the sense circuit.

19. The storage device of claim 16 , wherein calibrating the parameter comprises determining an interpolated value in between two of the applied values of the parameter.

20. The storage device of claim 19 , wherein calibrating the parameter comprises determining the interpolated value based on a histogram comprising a count of number of bits that flipped between a first page read when a first value is applied for the parameter and a second page read when a second value is applied for the parameter.

Assignees

• Intel Corp

Inventors

• Madraswala Aliasgar S
• Khakifirooz Ali
• Jaramillo Camila
• Egler John
• Mahuli Netra
• Chen Renjie
• Wakchaure Yogesh

Classifications

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0655 Primary

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title