Adaptive gate drive for a power switch transistor in a switching power converter

Patent metadata

Field	Value
Publication number	US-11689095-B2
Application number	US-202117145186-A
Country	US
Kind code	B2
Filing date	Jan 8, 2021
Priority date	Jan 8, 2021
Publication date	Jun 27, 2023
Grant date	Jun 27, 2023

Abstract

A gate drive control circuit is provided that charges a gate voltage of a power switch transistor during a power switch transistor on-time period. During a first portion of the on-time period, the gate drive control circuit charges the gate voltage through a relatively-low resistance. During a second portion of the on-time period, the gate drive control circuit charges the gate voltage through a relatively-high resistance. Finally, during a third portion of the on-time period, the gate drive control circuit charges the gate voltage through another relatively-low resistance.

First claim

We claim:

1. A gate drive control circuit for a power switch transistor in a switching power converter, comprising:
a gate drive circuit configured to charge a gate of the power switch transistor through a variable gate drive resistance;
an adaptive drive control circuit configured to command the gate drive circuit to use a first gate drive resistance during a first portion of a power switch transistor on-time period, a second gate drive resistance during a second portion of the power switch transistor on-time period, and a third gate drive resistance during a third portion of the power switch transistor on-time period; and
a gate voltage monitor configured to monitor a gate voltage of the power switch transistor, wherein the adaptive drive control circuit is further configured to end the first portion of the power switch transistor on-time period and transition to the second portion of the power switch transistor on-time period responsive to a comparison of the gate voltage of the power switch transistor to a first threshold voltage by the gate voltage monitor.

2. The gate drive control circuit of claim 1 , wherein the gate voltage monitor comprises:
a first comparator configured to compare the gate voltage of the power switch transistor to the first threshold voltage, wherein the adaptive drive control circuit is further configured to command the gate drive circuit to use the second gate drive resistance responsive to an assertion of an output signal from the first comparator, and wherein the second gate drive resistance is greater than the first gate drive resistance.

3. The gate drive control circuit of claim 2 , wherein the gate voltage monitor further comprises:
a second comparator configured to compare the gate voltage of the power switch transistor to a second threshold voltage.

4. The gate drive control circuit of claim 1 , wherein the adaptive gate drive control circuit is further configured to begin timing a maximum duration period at an initiation of the second portion of the power switch transistor on-time period and to trigger a transition from the second portion of the power switch transistor on-time period to the third portion of the power switch transistor on-time period responsive to an expiration of the maximum duration period.

5. The gate drive control circuit of claim 4 , wherein the adaptive drive control circuit is further configured to adapt the first threshold voltage responsive to a duration of the first portion of the power switch transistor on-time period and responsive to a duration of a second portion of the power switch transistor on-time period.

6. The gate drive control circuit of claim 4 , wherein the maximum duration period is less than a duration of a Miller plateau period for a gate voltage of the power switch transistor.

7. The gate drive control circuit of claim 6 , wherein the adaptive drive control circuit is further configured to adapt the first threshold voltage and a second threshold voltage so that the first threshold voltage is less than a Miller plateau value of the gate voltage of the power switch transistor and so that the second threshold voltage is greater than the Miller plateau value.

8. The gate drive control circuit of claim 1 ,
wherein the gate drive circuit includes a plurality of transistors coupled between the gate of the power switch transistor and a power supply node, wherein the adaptive drive control circuit comprises a logic circuit configured to command a first number of transistors in the plurality of transistors to switch on during the first portion of the power switch transistor on-time period and to command a second number of transistors in the plurality of transistors to switch on during the second portion of the power switch transistor on-time period.

9. The gate drive control circuit of claim 8 , wherein the first number is greater than the second number.

10. The gate drive control circuit of claim 8 , wherein each transistor in the plurality of transistors couples to the gate of the power switch transistor through a corresponding resistor.

11. A method of adapting a gate drive resistance for a power switch transistor in a switching power converter, comprising:
during an initial portion of a power switch transistor on-time period while a gate voltage of the power switch transistor is less than a first threshold voltage, charging a gate of the power switch transistor through a first resistance;
initiating a timing of a maximum delay period responsive to the gate voltage of the power switch transistor being greater than the first threshold voltage;
during a second portion of the power switch transistor on-time period prior to an expiration of the maximum delay period, charging the gate of the power switch transistor through a second resistance.

12. The method of claim 11 , further comprising:
responsive to an expiration of the maximum delay period, charging the gate of the power switch transistor through a third resistance during a third portion of the power switch transistor on-time period.

13. The method of claim 12 , wherein the third resistance is less than the second resistance.

14. The method of claim 11 , further comprising:
adapting the first threshold voltage so that a Miller plateau value of the gate voltage of the power switch transistor is greater than the first threshold voltage.

15. The method of claim 11 , further comprising:
discharging the gate voltage of the power switch transistor at an end of the power switch transistor on-time period.

16. A switching power converter, comprising:
an inductor;
a power switch transistor connected to the inductor; and
a gate drive control circuit configured to: charge a gate of the power switch transistor through a first resistance during a first portion of an on-time period for the power switch transistor, charge the gate of the power switch transistor through a second resistance during a second portion of the on-time period, and charge the gate of the power switch transistor through a third resistance during a third portion of the on-time period, wherein the second resistance is greater than the third resistance, wherein the gate drive control circuit comprises a first comparator configured to compare a gate voltage of the power switch transistor to a first threshold voltage; and a timer for timing a maximum duration period responsive to an initiation of the second portion of the on-time period.

17. The switching power converter of claim 16 , wherein the gate drive control circuit further comprises a logic circuit configured to select the first resistance during the first portion of the on-time period while an output signal from the first comparator indicates that the gate voltage of the power switch transistor is less than the first threshold voltage and to select for the second resistance during the second portion of the on-time period and prior to an expiration of the maximum duration period.

18. The switching power converter of claim 17 , wherein the logic circuit is further configured to select for the third resistance during the third portion of the on-time period responsive to an expiration of the maximum duration period.

Assignees

• Dialog Semiconductor Inc

Inventors

• Liu Wenduo
• Gong Huangxuan
• Kanagala Vijay
• Bui Hien

Classifications

• H02M1/08 Primary

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H03K17/04206

  in field-effect transistor switches · CPC title

• H02M1/44

  Circuits or arrangements for compensating for electromagnetic interference in converters or inverters · CPC title

• H02M3/33592

  having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer · CPC title

• H02M1/0029

  Circuits or arrangements for limiting the slope of switching signals, e.g. slew rate · CPC title