Display substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-11688745-B2
Application number	US-202117486583-A
Country	US
Kind code	B2
Filing date	Sep 27, 2021
Priority date	Sep 27, 2020
Publication date	Jun 27, 2023
Grant date	Jun 27, 2023

Abstract

A display substrate includes: a base, a plurality of pixel units arranged in columns in a first direction and in rows in a second direction, a plurality of data lines and first gate lines extending in the first direction, a plurality of second gate lines extending in the second direction, and at least one gate driver circuit connected to the first gate lines and located at a side of the display substrate parallel to the second direction. One pixel unit includes a TFT. The TFT is connected to one data line. In a column of pixel units, TFTs of any two adjacent pixel units are respectively located at first and second sides of a respective data line. Each second gate line is connected to a row of pixel units and at least one of the first gate lines. First gate lines connecting different second gate lines are different.

First claim

What is claimed is:

1. A display substrate, comprising:
a base;
a plurality of pixel units located on the base and arranged in columns in a first direction and in rows in a second direction, a pixel unit including a thin film transistor (TFT), the first direction intersecting with the second direction;
a plurality of data lines located on the base, arranged in the second direction and extending in the first direction, the TFT being connected to a data line; wherein in a column of pixel units, TFTs of any two adjacent pixel units are located at a first side and a second side of a respective data line, the first side and the second side are opposite sides of the same data line;
a plurality of first gate lines located on the base, arranged in the second direction and extending in the first direction;
a plurality of second gate lines located on the base, arranged in the first direction and extending in the second direction; each second gate line being connected to a row of pixel units and at least one of the plurality of first gate lines, first gate lines connected to different second gate lines being different; and
at least one gate driver circuit located on the base and connected to the plurality of first gate lines, the at least one gate driver circuit being disposed on a side of the display substrate parallel to the second direction;
wherein any two adjacent columns of pixel units have a gap therebetween, at least one data line is disposed in each gap, and one first gate line is disposed in each of at least part of gaps;
the at least one data line disposed in the gap includes one data line; and
the first gate line includes a plurality of first extension portions and a plurality of second extension portions arranged alternately, each first extension portion extends in the first direction, each second extension portion extends in the second direction, any two adjacent first extension portions are respectively located at opposite sides of a column of pixel units, and any two adjacent second extension portions are respectively located at opposite sides of a row of pixel units.

2. The display substrate according to claim 1 , wherein the pixel unit further includes an electrode connected to the TFT, the electrode and the TFT are stacked in a direction perpendicular to a plane where the base is located; the TFT includes a first electrode, a second electrode, and a gate, the plurality of second gate lines and the gate are disposed in the same layer, the display substrate further comprises:
an organic film located between the electrode and the TFT and having a plurality of via holes, wherein the plurality of first gate lines are located between the organic film and the electrode, each first gate line is connected to one second gate line through one of the plurality of via holes.

3. The display substrate according to claim 2 , wherein an orthogonal projection of each first gate line on the base is located between orthogonal projections of two adjacent data lines on the base.

4. The display substrate according to claim 1 , wherein the pixel unit further includes an electrode connected to the TFT, the electrode and the TFT are stacked in a direction perpendicular to a plane where the base is located, the TFT includes a first electrode, a second electrode, and a gate, the plurality of first gate lines are disposed on a side of the TFT away from the base, the plurality of second gate lines and the gate are disposed in the same layer, the display substrate further comprises:
an interlayer insulating layer located between the electrode and the TFT and having a plurality of via holes, each first gate line being connected to one second gate line through one of the plurality of via holes.

5. The display substrate according to claim 4 , wherein
a distance between orthogonal projections, on the base, of a first gate line and a data line in the same gap is less than a width of the data line.

6. The display substrate according to claim 4 , further comprising: a filling layer disposed in the via hole, the filling layer and the electrode being disposed in the same layer.

7. The display substrate according to claim 1 , wherein the pixel unit further includes an electrode connected to the TFT, the electrode and the TFT are stacked in a direction perpendicular to a plane where the base is located, the TFT includes a first electrode, a second electrode, and a gate, the plurality of first gate lines and the first electrode are disposed in the same layer, the plurality of second gate lines and the gate are disposed in the same layer, the display substrate further comprises:
an interlayer insulating layer located between the electrode and the TFT and having a plurality of via holes, each first gate line being connected to one second gate line through one of the plurality of via holes.

8. The display substrate according to claim 7 , further comprising: a filling layer disposed in the via hole, the filling layer and the electrode being disposed in the same layer.

9. The display substrate according to claim 7 , wherein
a distance between orthogonal projections, on the base, of a first gate line and a data line in the same gap is greater than a width of the data line.

10. The display substrate according to claim 1 , wherein
the pixel unit further includes a connection portion, an end of the connection portion is connected to a data line corresponding to the pixel unit, another end of the connection portion is connected to the TFT, and an orthogonal projection of each first gate line on the base is non-overlapping with an orthogonal projection of the connection portion on the base.

11. The display substrate according to claim 1 , wherein
in two data lines located at opposite sides of a column of pixel units, a TFT of any pixel unit is connected to one of the two data lines, and a first extension portion corresponding to the pixel unit and another of the two data lines are located in the same gap.

12. The display substrate according to claim 11 , wherein
the first gate line further includes a plurality of transition portions, a first extension portion and a second extension portion adjacent thereto are connected through one transition portion at a position where the TFT is located, and there is a predetermined angle between the transition portion and the second direction.

13. The display substrate according to claim 11 , wherein
the pixel unit further includes an electrode connected to the TFT and a compensation electrode connected to the electrode, the compensation electrode is closer to the another data line, which is in the same gap as the first extension portion corresponding to the pixel unit, than the electrode, so that a coupling capacitance between the electrode and the compensation electrode as a whole and one of the two data lines is equal to a coupling capacitance between the electrode and the compensation electrode as a whole and the another of the two data lines.

14. The display substrate according to claim 13 , wherein the compensation electrode has a hollow-out pattern.

15. The display substrate according to claim 1 , wherein
a width of the first gate line is greater than a width of the data line.

16. A display apparatus, comprising:
a display substrate according to claim 1 .

17. A display substrate, comprising:
a base;
a plurality of pixel units located on the base and arranged in columns in a first direction and in rows in a second direction, a pixel unit including a thin film transistor (TFT), the first direction intersecting with the second direction;
a plurality of da

Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd

Inventors

• Wang Cong
• Lee Seungmin
• Wang Xipeng
• Zhang Wei
• Xu Benzhi
• Zhou Xin
• Yang Tao
• Miao Yingmeng

Classifications

• H10D86/443

  adapted for preventing breakage, peeling or short circuiting · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title