Semiconductor device including an input/output circuit

Patent metadata

Field	Value
Publication number	US-11688686-B2
Application number	US-202117163869-A
Country	US
Kind code	B2
Filing date	Feb 1, 2021
Priority date	Jul 14, 2020
Publication date	Jun 27, 2023
Grant date	Jun 27, 2023

Abstract

A semiconductor device includes bumps and a plurality of input/output areas on a substrate. Each of the input/output areas include semiconductor elements on the substrate, lower wiring patterns connected to the semiconductor elements, and input/output pins above and connected to the lower wiring patterns. The semiconductor elements provide a logic circuit and a protection circuit. The bumps are above the lower wiring patterns and connected to the input/output pins by upper wiring patterns. The input/output areas include a first input/output area and a second input/output area. The input/output areas includes a first circuit area including the electrostatic discharge protection circuit and a second circuit area including the logic circuit. In the first input/output area, the input/output pin is in the first circuit area. In the second input/output area, the input/output pin is in the second circuit area.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a plurality of input/output areas,
each of the plurality of input/output areas including semiconductor elements on the substrate and providing a logic circuit and an electrostatic discharge protection circuit, lower wiring patterns connected to the semiconductor elements, input/output pins above the lower wiring patterns and connected to the lower wiring patterns, and upper wiring patterns; and
a plurality of bumps above the lower wiring patterns and connected to the input/output pins by the upper wiring patterns, wherein
the plurality of input/output areas include a first input/output area and a second input/output area,
each of the plurality of input/output areas includes a first circuit area and a second circuit area,
the first circuit area includes the electrostatic discharge protection circuit,
the second circuit area includes the logic circuit, the input/output pins of the first input/output area are in the first circuit area of the first input/output area, and
the input/output pins of the second input/output area are in the second circuit area of the second input/output area.

2. The semiconductor device of claim 1 , wherein
each of the plurality of input/output areas comprises an input/output wiring pattern in the second circuit area,
the input/output wiring pattern is connected to the logic circuit, and
the input/output wiring pattern is between the semiconductor elements and a corresponding one of the input/output pins in a direction perpendicular to an upper surface of the substrate.

3. The semiconductor device of claim 2 , wherein
the first input/output area and the second input/output area are adjacent to each other in one direction,
the one direction is parallel to the upper surface of the substrate, and
the electrostatic discharge protection circuit of the second input/output area is between the input/output wiring pattern of the first input/output area and the logic circuit of the second input/output area in the one direction.

4. The semiconductor device of claim 2 , wherein a distance between one of the input/output pins and the input/output wiring pattern in the first input/output area, in one direction parallel to the upper surface of the substrate, is greater than a distance between one of the input/output pins and the input/output wiring pattern in the second input/output area.

5. The semiconductor device of claim 1 , wherein
the plurality of bumps comprise a first bump connected to the first input/output area and a second bump connected to the second input/output area,
the first input/output area and the second input/output area are adjacent to each other in a first direction parallel to an upper surface of the substrate, and
at least one of the first bump and the second bump is between one of the input/output pins of the first input/output area and one of the input/output pins of the second input/output area.

6. The semiconductor device of claim 5 , wherein at least one of the first bump and the second bump overlaps at least one of the first input/output area and the second input/output area.

7. The semiconductor device of claim 6 , wherein
at least one of the first bump and the second bump has an overlapping area and a non-overlapping area,
the overlapping area overlaps at least one of the first input/output area and the second input/output area,
the non-overlapping area that does not overlap the plurality of input/output areas, and
an area of the overlapping area is greater than an area of the non-overlapping area.

8. The semiconductor device of claim 1 , wherein a first lower wiring pattern among the lower wiring patterns in the second input/output area traverses a boundary between the first circuit area and the second circuit area.

9. The semiconductor device of claim 8 , wherein the first lower wiring pattern is in an uppermost layer among a plurality of layers including the lower wiring patterns.

10. The semiconductor device of claim 1 , wherein
the plurality of input/output areas further comprise a third input/output area, and
in the third input/output area, an input/output pin overlaps a boundary between the first circuit area and the second circuit area.

11. A semiconductor device comprising:
a substrate having a first area and a second area surrounded by the first area;
a plurality of input/output areas in the first area,
the plurality of input/output areas arranged in a first direction parallel to an upper surface of the substrate and in a second direction different from the first direction,
each of the plurality of input/output areas including semiconductor elements providing an input/output circuit, lower wiring patterns connected to the semiconductor elements, an input/output pin connected to the lower wiring patterns, and upper wiring patterns,
such that the plurality of input/output areas have input/output pins;
a core region in the second area; and
a plurality of bumps connected to the input/output pins by the upper wiring patterns at a same height as the input/output pins, wherein
the lower wiring patterns provide an input/output wiring pattern connecting the input/output circuit to the core region, and
the plurality of input/output areas include a first input/output area and a second input/output area,
a distance between the input/output wiring pattern and the input/output pin in the first input/output area is a first distance,
a distance between the input/output wiring pattern and the input/output pin in the second input/output area is a second distance, and
the second distance is different from the first distance.

12. The semiconductor device of claim 11 , wherein
the input/output pin in the first input/output area has a first height in the first direction and a first width in the second direction,
the input/output pin in the second input/output area has a second height and a second width,
the second height is lower than the first height in the first direction, and
the second width is greater than the first width in the second direction.

13. The semiconductor device of claim 12 , wherein an area of the input/output pin included in the first input/output area is the same as an area of the input/output pin included in the second input/output area.

14. The semiconductor device of claim 12 , wherein
the input/output pin included in the first input/output area is on an upper portion of one of an electrostatic discharge protection circuit and a logic circuit included in the first input/output area, and
the input/output pin included in the second input/output area overlaps a boundary between an electrostatic discharge protection circuit and a logic circuit included in the second input/output area.

15. The semiconductor device of claim 11 , wherein
each of the plurality of input/output areas has a first boundary and a second boundary that are parallel to an edge of the substrate and are separated from each other,
the second boundary is closer to the core region than the first boundary, and
in each of the plurality of input/output areas, the input/output wiring pattern is closer to the second boundary than the first boundary.

16. The semiconductor device of claim 15 , wherein, in at least one of the plurality of input/output areas, a distance between the input/output pin and the first boundary is the same as a distance between the input/output pin and the second boundary.

17. The semiconductor device of claim 11 , wherein the plurality of input/output areas comprise:
horizontal input/output areas in whic

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Woonki
• Kim Minsic
• Oh Seunghun
• Kim Jinhyeong
• An Junyeong
• Lee Jooyeon
• Pyo Sangwoo

Classifications

• H10W72/248

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W70/654

  Top-view layouts · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title