Method for modeling sequence impedance of modular multilevel converter under phase locked loop coupling

Patent metadata

Field	Value
Publication number	US-11687699-B2
Application number	US-202117771967-A
Country	US
Kind code	B2
Filing date	Dec 11, 2021
Priority date	Jan 28, 2021
Publication date	Jun 27, 2023
Grant date	Jun 27, 2023

Abstract

The present invention discloses a method for modeling sequence impedance of a modular multilevel converter (MMC) under phase locked loop (PLL) coupling. The method includes the following steps: S1, establishing a circuit topology model; S2, establishing a PLL output characteristic model; S3, establishing a PI controller output control small signal model under a dq axis; S4, deducing a modulation small signal; and S5, calculating MMC port impedance. According to the method, a precise MMC port impedance model is established by analyzing a double mirror frequency coupling effect in the output of a modulation signal in a control link caused by a phase angle disturbance and comprehensively considering the combination of the multi-harmonic coupling effect of an MMC. On one hand, the proposed modeling method aims at a common MMC adopting current closed-loop control, in which a half-bridge sub-module is adopted, a circuit topological structure and a control structure are both more common, and a mathematical model is easy to establish. On the other hand, the physical significance of an impedance analysis method is clear, the modeling process is modular and is easy to understand and implement, and the inverter port impedance can be measured on site, so that the correctness of theoretical modeling can be conveniently verified.

First claim

What is claimed is:

1. A method for modeling sequence impedance of a modular multilevel converter (MMC) under phase locked loop (PLL) coupling, comprising the following steps:
S1, establishing a circuit topology model
dividing a current-controlled MMC grid-connected system into two parts: a circuit topology and a control link, and acquiring relevant parameters;
S2, establishing a PLL output characteristic model
establishing a relationship model between a PLL output phase angle small signal Δθ and a q-axis power grid voltage small signal of a power grid and a PLL controller G pll according to an abc/dq transformation formula under a phase angle disturbance and a PLL control signal path;
S3, establishing a PI controller output control small signal model under a dq axis
establishing a relationship model between control small signals Δe d and Δe q under the dq axis and current small signals Δi d and Δi q under the dq axis, current steady-state operating points i d and i q under the dq axis, and the phase angle small signal Δθ and a current controller G i according to a current closed-loop control path;
S4, deducing a modulation small signal
obtaining modulation small signals of frequency f p output by a phase-a control system and frequency f p ∓2f l generated under the action of PLL coupling according to the control small signals Δe d and Δe q and in consideration of a dq/abc transformation formula under a phase angle disturbance;
S5, calculating MMC port impedance
substituting a system model into a harmonic state space matrix, calculating a current response Δi g when injecting a voltage disturbance Δu g , and finally calculating MMC port impedance according to a port impedance definition.

2. The method for modeling sequence impedance of the MMC under PLL coupling according to claim 1 , wherein the establishing a circuit topology model in S1 is as follows:

{

Ri
g

+

L
⁢

di
g

dt

+

2
⁢

u
g

=

n
l

⁢

u
cl
∑

-

n
u

⁢

u
cu
∑

2
⁢

Ri
c

+

2
⁢
L
⁢

di
c

dt

+

n
l

⁢

u
cl
∑

+

n
u

⁢

u
cu
∑

=

U
dc

C
arm

⁢

du
cu
∑

dt

=

n
u

(

i
c

+

i
g

2

)

C
arm

Assignees

• Univ Southeast

Inventors

• Deng Fujin
• Zhou Yun
• Zhang Hanlu
• Liu Chengkai
• Zhang Jianzhong

Classifications

• H02J2103/30

  Simulating, planning, modelling, reliability check or computer assisted design [CAD] of electric power networks · CPC title

• H02J3/381

  Dispersed generators · CPC title

• H02J2203/20

  Electricity · mapped topic

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• H02M1/08 Primary

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title