Programmable state machine for a hardware performance monitor

Patent metadata

Field	Value
Publication number	US-11687435-B2
Application number	US-202117380375-A
Country	US
Kind code	B2
Filing date	Jul 20, 2021
Priority date	Jul 20, 2021
Publication date	Jun 27, 2023
Grant date	Jun 27, 2023

Abstract

A processing unit can include a performance monitor for monitoring the performance of the processing unit and associated sub-units. The performance monitor can include a state machine. The state machine can be implemented via state machine data entries stored in a memory associated with the performance monitor. A state machine data entry includes information indicating a state transition condition and output signals. The state transition condition includes a current state and input signals required to meet the condition. The output signals include a next state, one or more counter actions, and one or more triggers. The performance monitor implements logic circuits that determine, based on input signals and the state machine data entries, the next state to transition and associated output signals. The state machine data entries can be written and re-written by a user.

First claim

What is claimed is:

1. A method, comprising:
receiving a set of one or more signals;
generating a first input based on the set of one or more signals and a first input mask associated with a first state transition condition, wherein the first input mask and the first state transition condition are stored in a first data entry in a memory associated with a performance monitor;
determining, based on the first input and a current state, that the first state transition condition is satisfied; and
in response to determining that the first state transition condition is satisfied, transitioning the performance monitor from the current state to a first state, wherein the first state is stored in the memory and associated with the first state transition condition.

2. The method of claim 1 , wherein the first state transition condition comprises a tag.

3. The method of claim 2 , wherein determining that the first state transition condition is satisfied comprises determining that a combination of the first input and the current state matches the tag.

4. The method of claim 3 , wherein the tag comprises a first portion for comparison to the first input and a second portion for comparison to the current state.

5. The method of claim 1 , further comprising:
in response to determining that the first state transition condition is satisfied, performing an operation on a counter.

6. The method of claim 4 , wherein the first data entry comprises one or more output signals including a signal indicating the operation to perform on the counter, and wherein performing the operation on the counter comprises transmitting the signal indicating the operation to perform on the counter to a logic circuit configured to perform the operation on the counter.

7. The method of claim 1 , wherein the first data entry further comprises a trigger signal, the method further comprising:
in response to determining that the first state transition condition is satisfied, outputting the trigger signal to a logic analyzer.

8. The method of claim 1 , further comprising:
receiving a second set of one or more signals;
generating a second input based on the second set of one or more signals and a second input mask associated with a second state transition condition, wherein the second input mask and the second state transition condition are stored in a second data entry in the memory;
determining, based on the second input and the first state, that the second state transition condition is satisfied; and
in response to determining that the second state transition condition is satisfied, transitioning the performance monitor from the first state to a second state, wherein the second state is stored in the memory and associated with the second state transition condition.

9. The method of claim 1 , wherein the memory comprises a content-addressable memory.

10. The method of claim 1 , further comprising replacing the first data entry in the memory with a second data entry, wherein the second data entry comprises a second state transition condition and a second input mask.

11. A system, comprising:
a processor comprising a set of logic circuits associated with a state machine; and
a memory included in the processor;
wherein the processor:
receives, via the set of logic circuits, a set of one or more signals;
generates, via the set of logic circuits, a first input based on the set of one or more signals and a first input mask associated with a first state transition condition, wherein the first input mask and the first state transition condition are stored in a first data entry in the memory;
determines, via the set of logic circuits, based on the first input and a current state, that the first state transition condition is satisfied; and
in response to determining that the first state transition condition is satisfied, transitions, via the set of logic circuits, the processor from the current state to a first state, wherein the first state is stored in the memory and associated with the first state transition condition,
wherein the first state transition condition, the current state, and the first state are associated with the state machine.

12. The system of claim 11 , wherein the memory comprises a content-addressable memory.

13. The system of claim 11 , wherein the processor replaces the first data entry in the memory with a second data entry, wherein the second data entry comprises a second state transition condition associated with the state machine and a second input mask.

14. The system of claim 11 , wherein the processor, in response to determining that the first state transition condition is satisfied, performs, via the set of logic circuits, an operation on a counter associated with the state machine.

15. The system of claim 14 , wherein the first data entry comprises one or more output signals, the one or more output signals including a signal indicating the operation to perform on the counter, wherein the processor comprises a logic circuit associated with the counter, and wherein performing the operation on the counter comprises transmitting the signal indicating the operation to perform on the counter to the logic circuit associated with the counter.

16. The system of claim 11 , wherein the first data entry further comprises a trigger signal, wherein the processor comprises a logic analyzer; and wherein the processor, in response to determining that the first state transition condition is satisfied, further outputs, via the set of logic circuits, the trigger signal to the logic analyzer.

17. The system of claim 11 , wherein the processor:
receives, via the set of logic circuits, a second set of one or more signals;
generates, via the set of logic circuits, a second input based on the second set of one or more signals and a second input mask associated with a second state transition condition, wherein the second input mask and the second state transition condition are stored in a second data entry in the memory;
determines, via the set of logic circuits, based on the second input and the first state, that the second state transition condition is satisfied; and
in response to determining that the second state transition condition is satisfied, transitions, via the set of logic circuits, the processor from the first state to a second state, wherein the second state is stored in the memory and associated with the second state transition condition.

18. A non-transitory computer-readable medium storing program instructions that, when executed by a processor, cause the performance monitor to perform the steps of:
receiving a set of one or more signals;
generating a first input based on the set of one or more signals and a first input mask associated with a first state transition condition, wherein the first input mask and the first state transition condition are stored in a first data entry in a memory associated with a performance monitor;
determining, based on the first input and a current state, that the first state transition condition is satisfied; and
in response to determining that the first state transition condition is satisfied, transitioning the performance monitor from the current state to a first state, wherein the first state is stored in the memory and associated with the first state transition condition.

19. The non-transitory computer-readable medium of claim 18 , wherein the memory comprises a content-addressable memory.

20. The non-transitory computer-readable medium of claim 18 , wherein the steps further comprise

Assignees

• Nvidia Corp

Inventors

• Zhou Gongyu
• Kamalapurkar Shounak
• Kulkarni Yogesh
• Ogletree Thomas Melvin
• Ranade Abhijat

Classifications

• G06F11/3409 Primary

  for performance assessment · CPC title

• G06F11/3003

  Monitoring arrangements specially adapted to the computing system or computing system component being monitored · CPC title

• G06F11/348 Primary

  Circuit details, i.e. tracer hardware · CPC title

• G06F2201/88

  Monitoring involving counting · CPC title

• G06F2201/835

  Timestamp · CPC title