Soft FEC with parity check

Patent metadata

Field	Value
Publication number	US-11683124-B2
Application number	US-202217677481-A
Country	US
Kind code	B2
Filing date	Feb 22, 2022
Priority date	Aug 30, 2017
Publication date	Jun 20, 2023
Grant date	Jun 20, 2023

Abstract

A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.

First claim

What is claimed is:

1. A data transmission device, comprising:
a de-interleaver configured to (i) receive, from a host device at a first data rate, a data stream including encoded data, (ii) de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and (iii) output the plurality of FEC data streams at a second data rate less than the first data rate;
a plurality of interleavers each configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks; and
encoder circuitry configured to
generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and
output the FEC blocks at the second data rate.

2. The data transmission device of claim 1 , wherein the de-interleaver is an FEC lane de-interleaver configured to de-interleave the data stream into four FEC data streams.

3. The data transmission device of claim 1 , further comprising an alignment marker framer configured to frame the plurality of FEC data streams.

4. The data transmission device of claim 1 , wherein the first data blocks and the second data blocks correspond to even data blocks and odd data blocks, respectively.

5. The data transmission device of claim 4 , each of the plurality of interleavers comprising a delay line configured to delay the first data blocks to generate the even data blocks.

6. The data transmission device of claim 5 , each of the plurality of the plurality of interleavers comprising a multiplexer configured to output the even data blocks and the odd data blocks.

7. The data transmission device of claim 1 , further comprising a deskew circuitry configured to remove data misalignment from the plurality FEC data streams as received from the de-interleaver.

8. The data transmission device of claim 1 , further comprising a transmission circuitry configured to output the FEC blocks to a pulse-amplitude modulation (PAM) channel.

9. A method, comprising:
receiving, from a host device at a first data rate, a data stream including encoded data;
de-interleaving the data stream into a plurality of forward error correction (FEC) data streams;
outputting the plurality of FEC data streams at a second data rate less than the first data rate;
interleaving, with each of a plurality of interleavers, a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks;
generating, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks; and
outputting the FEC blocks at the second data rate.

10. The method of claim 9 , further comprising de-interleaving the data stream into four FEC data streams.

11. The method of claim 9 , further comprising framing the plurality of FEC data streams using alignment markers in the FEC data streams.

12. The method of claim 9 , wherein the first data blocks and the second data blocks correspond to even data blocks and odd data blocks, respectively.

13. The method of claim 12 , further comprising delaying the first data blocks to generate the even data blocks.

14. The method of claim 13 , further comprising outputting the even data blocks and the odd data blocks using a multiplexer.

15. The method of claim 9 , further comprising removing data misalignment from the plurality FEC data streams as received from a de-interleaver.

16. The method of claim 9 , further comprising outputting the FEC blocks to a pulse-amplitude modulation (PAM) channel.

Assignees

• Marvell Asia Pte Ltd

Inventors

• Riani Jamal
• Smith Benjamin
• Shvydun Volodymyr
• Swaminathan Srinivas
• Farhoodfar Arash

Classifications

• H04L1/0055

  MAP-decoding · CPC title

• H04L1/0071 Primary

  Use of interleaving (interleaving per se H03M13/27) · CPC title

• H04L1/0046

  Code rate detection or code type detection (H04L1/0038 takes precedence; detection of the data rate H04L25/0262; for packet format H04L1/0091) · CPC title

• H04L1/0042

  Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape (H04L1/0067 takes precedence) · CPC title

• H04L1/0063

  Single parity check · CPC title