Instant RF overvoltage protection element

Patent metadata

Field	Value
Publication number	US-11683056-B2
Application number	US-202117319592-A
Country	US
Kind code	B2
Filing date	May 13, 2021
Priority date	May 13, 2021
Publication date	Jun 20, 2023
Grant date	Jun 20, 2023

Abstract

A peak detector includes an asymmetrical latch having a first input and a second input; and a CMOS converter having a first input coupled to a first output of the asymmetrical latch, a second input coupled to a second output of the asymmetrical latch, and an output.

First claim

What is claimed is:

1. A peak detector comprising:
an asymmetrical latch having a first input and a second input; and
a CMOS converter having a first input coupled to a first output of the asymmetrical latch, a second input coupled to a second output of the asymmetrical latch, and an output.

2. The peak detector of claim 1 , further comprising a preamplifier having a first output coupled to the first input of the asymmetrical latch and a second output coupled to the second input of the asymmetrical latch.

3. The peak detector of claim 2 , further comprising a first capacitor coupled between a first RF input and a first input of the preamplifier.

4. The peak detector of claim 3 , further comprising a second capacitor coupled between a second RF input and a second input of the preamplifier.

5. The peak detector of claim 3 , further comprising a first resistor coupled between a common mode voltage source or a reference voltage source and the first input of the preamplifier.

6. The peak detector of claim 5 , further comprising a second resistor coupled between the common mode voltage source and the second input of the preamplifier.

7. The peak detector of claim 2 , wherein the preamplifier is configured for receiving a reference voltage or common mode voltage.

8. The peak detector of claim 7 , further comprising a digital-to-analog converter coupled between a reference voltage source or a common mode voltage source and the preamplifier.

9. The peak detector of claim 1 , wherein the asymmetrical latch is configured to latch only in response to a rising edge input signal crossing a latch threshold.

10. The peak detector of claim 1 , wherein a delay of the peak detector is less than two nanoseconds.

11. The peak detector of claim 1 , further comprising a buffer amplifier interposed between the asymmetrical latch and the CMOS converter.

12. A method comprising:
amplifying a differential input signal to provide an amplified differential signal;
asymmetrically latching the amplified differential signal to provide a latched differential signal; and
converting the latched differential signal into a CMOS-level output signal.

13. The method of claim 12 , wherein asymmetrically latching the amplified differential signal comprises latching only in response to a rising edge of a component of the amplified differential signal crossing a latch threshold.

14. The method of claim 13 , wherein a delay between the rising edge of the component of the amplified differential signal crossing the latch threshold to providing the CMOS-level output signal is less than two nanoseconds.

15. The method of claim 13 , further comprising adjusting the latch threshold in response to a first control voltage.

16. The method of claim 15 , further comprising adjusting the latch threshold in response to a second control voltage different from the first control voltage.

17. The method of claim 12 , further removing a DC component of the differential input signal before amplifying the differential input signal.

18. The method of claim 12 , further comprising buffering the latched differential signal before converting the latched differential signal into the CMOS-level output signal.

19. A system comprising:
a first amplifier in communication with an attenuator; and
a voltage detector coupled to an output of the first amplifier, and coupled to a control input of the attenuator, wherein the voltage detector comprises a second amplifier, an asymmetrical latch, and a CMOS converter.

20. The system of claim 19 , further comprising a first resistor coupled between a common mode voltage source and a first positive input of the second amplifier, and a second resistor coupled between the common mode voltage source and a second positive input of the second amplifier.

Assignees

• Infineon Technologies Ag

Inventors

• Wickmann Andreas
• Leitner Thomas

Classifications

• H04B17/21

  for calibration; for correcting measurements · CPC title

• H04B1/10 Primary

  Means associated with receiver for limiting or suppressing noise or interference · CPC title

• G01R21/01

  in circuits having distributed constants (G01R21/04, G01R21/07, G01R21/09, G01R21/12 take precedence) · CPC title

• H04B17/22

  for calibration of the receiver components · CPC title

• H03F2203/45596

  the IC comprising one or more biasing resistors · CPC title