Through-vias and methods of forming the same

Patent metadata

Field	Value
Publication number	US-11682583-B2
Application number	US-201816215792-A
Country	US
Kind code	B2
Filing date	Dec 11, 2018
Priority date	Dec 28, 2012
Publication date	Jun 20, 2023
Grant date	Jun 20, 2023

Abstract

An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring.

First claim

What is claimed is:

1. A method comprising:
forming a first through-via extending from a first side of a semiconductor substrate into the semiconductor substrate, wherein the semiconductor substrate comprises a first surface on the first side;
polishing the semiconductor substrate so that a second surface of the semiconductor substrate is formed, with the second surface being opposite to the first surface, wherein the semiconductor substrate comprises a semiconductor material continuously extends from the first surface to the second surface, and wherein after the polishing, the first through-via is revealed through the second surface;
etching the semiconductor substrate from a second side of the semiconductor substrate to form a first through-opening, wherein the first side and the second side are opposite sides of the semiconductor substrate;
filling the first through-opening with a dielectric material to form a dielectric region; and
forming a second through-via penetrating through the dielectric region.

2. The method of claim 1 , wherein at a time after the second through-via is formed, a layer of the dielectric material overlaps both of the semiconductor substrate and the first through-via.

3. The method of claim 1 further comprising:
after the semiconductor substrate is polished and before the first through-opening is formed, depositing a dielectric layer contacting the second surface; and
forming a conductive ring penetrating through the dielectric layer and the semiconductor substrate.

4. The method of claim 1 further comprising:
etching the dielectric region to form a second plurality of through-openings, wherein a plurality of portions of the dielectric region inside the semiconductor substrate are removed by the etching the dielectric region; and
filling the second plurality of through-openings with a conductive material to form a second plurality of through-vias separated from each other by the dielectric material, wherein each of the second plurality of through-vias is encircled by, and is in contact with, the dielectric material.

5. The method of claim 1 , wherein the dielectric material fully fills the first through-opening.

6. The method of claim 1 further comprising:
before the filling the first through-opening with the dielectric material, forming a conductive ring in the first through-opening, wherein the conductive ring is on a sidewall of the semiconductor substrate facing the first through-opening, and wherein at a time the second through-via is formed, a third through-via is formed simultaneously, and wherein both of the second through-via and the third through-via are encircled by the conductive ring.

7. The method of claim 1 , wherein the filling the first through-opening with the dielectric material comprising filling a polymer in the first through-opening.

8. The method of claim 1 , wherein the first side is a front side of the semiconductor substrate, with an active device formed at the first surface of the semiconductor substrate.

9. The method of claim 1 , wherein the first through-via extends into a semiconductor material of the semiconductor substrate, and the first through-opening penetrates through the semiconductor material of the semiconductor substrate.

10. The method of claim 1 further comprising, after the forming the first through-opening and before the filling the first through-opening with the dielectric material:
forming an isolation ring in the first through-opening, wherein the isolation ring is on a sidewall of the semiconductor substrate; and
forming a conductive ring in the first through-opening, wherein the conductive ring is encircled by the isolation ring.

11. A method comprising:
forming a first through-via penetrating completely through a semiconductor substrate, wherein a dielectric ring is between, and is in contact with, the semiconductor substrate and the first through-via;
forming a second through-via penetrating through the semiconductor substrate, wherein the second through-via is separated from the semiconductor substrate by a dielectric region and a conductive ring, and wherein the first through-via and the second through-via are formed from opposite directions of the semiconductor substrate;
forming a first redistribution line contacting the first through-via; and
forming a plurality of redistribution lines at a same level, wherein the plurality of redistribution lines comprise a second redistribution line contacting the second through-via.

12. The method of claim 11 further comprising forming an isolation ring separating the conductive ring from the semiconductor substrate.

13. The method of claim 11 , wherein the first through-via and the second through-via are formed in separate formation processes.

14. A method comprising:
forming a first through-via extending from a front surface of a semiconductor substrate into the semiconductor substrate;
forming a metal pad on a front side of the semiconductor substrate;
performing a backside grinding from a backside of the semiconductor substrate to reveal the first through-via, wherein after the backside grinding, the semiconductor substrate has a back surface opposite to the front surface;
forming a dielectric region extending from the back surface to the front surface of the semiconductor substrate;
etching the dielectric region and a dielectric layer to form a plurality of through-openings, wherein the dielectric layer is on the front side of the semiconductor substrate, and wherein the metal pad is revealed to the through-opening; and
filling the plurality of through-openings with a conductive material to form a plurality of through-vias separated from each other, wherein each of the plurality of through-vias is encircled by, and is in physical contact with, the dielectric region.

15. The method of claim 14 further comprising, in a same process for forming the dielectric region, forming an additional dielectric layer covering the semiconductor substrate, wherein the dielectric layer further overlaps the first through-via.

16. The method of claim 14 , wherein the etching the dielectric region is performed from the backside of the semiconductor substrate, wherein the backside is opposite to the front side of the semiconductor substrate, with the front surface being on the front side.

17. The method of claim 16 further comprising:
etching the semiconductor substrate to form an opening; and
fill the opening with a dielectric material to form the dielectric region, wherein at a time the dielectric region is formed, the opening is fully filled.

18. The method of claim 11 further comprising, when the second through-via is formed, simultaneously form a third through-via, wherein both of the second through-via and the third through-via are encircled by, and are in contact with, the dielectric region.

19. The method of claim 14 , wherein the filling the plurality of through-openings comprises plating the conductive material.

20. The method of claim 14 , wherein the forming the dielectric region comprises applying a polymer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Chung-Hao
• Yeh En-Hsiang
• Wang Chuei-Tang

Classifications

• H10W20/2128

  Coaxial through-semiconductor vias · CPC title

• H10W20/212

  Top-view shapes or dispositions, e.g. top-view layouts of the vias · CPC title

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title