Conservative rasterization

Patent metadata

Field	Value
Publication number	US-11682147-B2
Application number	US-202217665409-A
Country	US
Kind code	B2
Filing date	Feb 4, 2022
Priority date	Jun 29, 2018
Publication date	Jun 20, 2023
Grant date	Jun 20, 2023

Abstract

Conservative rasterization hardware comprises hardware logic arranged to perform an edge test calculation for each edge of a primitive and for each corner of each pixel in a microtile. Outer coverage results are determined, for a particular pixel and edge, by combining the edge test results for the four corners of the pixel and the particular edge in an OR gate. Inner coverage results are determined, for a particular pixel and edge, by combining the edge test results for the four corners of the pixel and the particular edge in an AND gate. An overall outer coverage result for the pixel and the primitive is calculated by combining the outer coverage results for the pixel and each of the edges of the primitive in an AND gate. The overall inner coverage result for the pixel is calculated in a similar manner.

First claim

What is claimed is:

1. A graphics processing pipeline comprising conservative rasterization hardware, and wherein the conservative rasterization hardware comprises:
a plurality of first hardware sub-units each arranged to calculate, for a different edge of a primitive, a plurality of coverage results for an edge for each pixel in a microtile, and
a plurality of second hardware sub-units each arranged to calculate, for a different pixel in a microtile, a plurality of coverage results for the primitive;
wherein each first hardware sub-unit comprises:
a plurality of OR logic blocks each configured to perform an OR operation, and each arranged to receive as inputs four values from edge test calculation hardware, one for each corner of a pixel, and wherein an output of the OR logic block is an outer coverage result for the pixel and the edge, and
a first plurality of AND logic blocks each configured to perform an AND operation, and each arranged to receive as inputs four values from the edge test calculation hardware, one for each corner of the pixel and wherein an output of the AND logic block is an inner coverage result for the pixel and the edge;

and wherein each second hardware sub-unit comprises:
a second plurality of AND logic blocks, each arranged to receive as inputs an outer or an inner coverage result for a pixel and each of the edges, one from each of the first hardware sub-units and wherein an output of the AND logic block is a corresponding outer or inner coverage result for the pixel and the primitive.

2. The graphics processing pipeline according to claim 1 , comprising edge test calculation hardware arranged to calculate, for each corner of the pixels in the microtile a value indicating whether the pixel corner is to the left of the edge, wherein the edge test calculation hardware comprises one or more hardware arrangements each arranged to perform an edge test using a sum-of-products, each hardware arrangement comprising:
a microtile component hardware element comprising hardware logic arranged to calculate a first output using the sum-of-products and coordinates of a microtile within a tile in the rendering space;
a plurality of pixel component hardware elements, each comprising hardware logic arranged to calculate one of a plurality of second outputs using the sum-of-products and coordinates for different pixel corners defined relative to an origin of the microtile;
a plurality of adders arranged to generate a plurality of output results for the sum-of-products in parallel by combining, for each output result, a different combination of the first output and one of the plurality of second outputs.

3. The graphics processing pipeline according to claim 2 , wherein each hardware arrangement further comprises:
a subsample component hardware element, the subsample component hardware element comprising hardware logic arranged to output a fixed third output,

and wherein the plurality of adders are arranged to generate the plurality of output results by combining, for each output result, the third output and the different combination of the first output and one of the plurality of second outputs.

4. The graphics processing pipeline according to claim 3 , wherein the fixed third output is set to zero.

5. The graphics processing pipeline according to claim 2 , wherein one or more of the hardware arrangements further comprises:
a plurality of multiplexers arranged to select the different combinations of the first output and one of the plurality of second outputs.

6. The graphics processing pipeline according to claim 2 , wherein the plurality of adders comprises:
a plurality of addition and comparison elements, each addition and comparison element arranged to generate a different one of the plurality of output results by combining a different combination of the first output and one of the plurality of second outputs.

7. The graphics processing pipeline according to claim 6 , wherein one or more of the hardware arrangements further comprises a first plurality of multiplexers, each of the multiplexers in the first plurality of multiplexers having a plurality of inputs and an output, wherein each input is arranged to receive a different one of the plurality of second outputs from the plurality of pixel component hardware elements and the multiplexer is arranged to select one of the received second outputs and output the selected second output to one of the plurality of addition and comparison elements via the output.

8. The graphics processing pipeline according to claim 2 , wherein the plurality of adders comprises a first subset of the plurality of adders and a second subset of the plurality of adders,
wherein each of the pixel component hardware elements further comprises an input for receiving the first output from the microtile component hardware element and at least one of the first subset of the plurality of adders arranged to sum the first output received from the microtile component hardware element and the second output calculated by the pixel component hardware element to generate an intermediate result, and
wherein the second subset of the plurality of adders comprises:
a plurality of comparison elements, each comparison element arranged to generate a different one of the plurality of output results by evaluating a different one of the intermediate results.

9. The graphics processing pipeline according to claim 8 , wherein one or more of the hardware arrangements further comprises a first plurality of multiplexers, each of the multiplexers in the first plurality of multiplexers having a plurality of inputs and an output, wherein each input is arranged to receive a different one of the intermediate results from the plurality of pixel component hardware elements and the multiplexer is arranged to select one of the received intermediate results and output the selected intermediate result to one of the plurality of comparison elements via the output.

10. The graphics processing pipeline according to claim 1 , comprising edge test calculation hardware arranged to calculate, for each corner of the pixels in the microtile a value indicating whether the pixel corner is to the left of the edge, wherein the edge test calculating hardware comprises one or more hardware arrangements each arranged to perform an edge test using a sum-of-products, each hardware arrangement comprising:
a microtile component hardware element comprising hardware logic arranged to calculate a first output using the sum-of-products and coordinates of a microtile within a tile in the rendering space;
a plurality of pixel component hardware elements, each comprising:
hardware logic arranged to calculate one of a plurality of second outputs using the sum-of-products and coordinates for different pixel corners defined relative to an origin of the microtile;
an input for receiving the first output from the microtile component hardware element;
a plurality of adders arranged to sum the first output received from the microtile component hardware element and the second output calculated by the pixel component hardware element to generate an intermediate result; and
a comparison element arranged to generate one of the plurality of output results by evaluating the intermediate result.

11. The graphics processing pipeline of claim 1 , wherein the graphics processing system is embodied in hardware on an integrated circuit.

12. A method of manufacturing, using an integrated circuit manufacturing system, a graphics processing pipeline as claimed in claim 1 , comprising inputting to said system a computer readable dataset description of said graphics processing pipeline and causing said

Assignees

• Imagination Tech Ltd

Inventors

• Van Benthem Casper

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T11/40 Primary

  Filling planar surfaces by adding surface attributes, e.g. adding colours or textures · CPC title

• G06T15/205

  Image-based rendering · CPC title

• G06T7/13 Primary

  Edge detection · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title