Opto electrical test measurement system for integrated photonic devices and circuits

Patent metadata

Field	Value
Publication number	US-11680870-B2
Application number	US-202117516165-A
Country	US
Kind code	B2
Filing date	Nov 1, 2021
Priority date	Apr 20, 2016
Publication date	Jun 20, 2023
Grant date	Jun 20, 2023

Abstract

An optical testing circuit on a wafer includes an optical input configured to receive an optical test signal and photodetectors configured to generate corresponding electrical signals in response to optical processing of the optical test signal through the optical testing circuit. The electrical signals are simultaneously sensed by a probe circuit and then processed. In one process, test data from the electrical signals is simultaneously generated at each step of a sweep in wavelength of the optical test signal and output in response to a step change. In another process, the electrical signals are sequentially selected and the sweep in wavelength of the optical test signal is performed for each selected electrical signal to generate the test data.

First claim

The invention claimed is:

1. An integrated circuit including a testing circuit, said testing circuit comprising an optical test circuit having:
an optical input configured to receive an optical test signal;
a test channel configured to receive said optical test signal, split the optical test signal into a first optical signal and a second optical signal, and produce an optical test output signal in response to processing of the first optical signal through at least one optical device under test circuit, said test channel further including a first photodetector coupled to receive said optical test output signal and generate a first electrical signal and a second photodetector coupled to receive said second optical signal and generate a second electrical signal; and
first and second electrical outputs for outputting said first and second electrical signals, respectively.

2. The integrated circuit of claim 1 , wherein the at least one optical device under test circuit comprises a plurality of series coupled optical device under test circuits.

3. The integrated circuit of claim 1 , wherein the test channel comprises a further photodetector coupled to receive the optical test signal and generate a further electrical signal, the optical test circuit further including a further electrical output for outputting said further electrical signal.

4. The integrated circuit of claim 1 , wherein the test channel comprises a further photodetector coupled to receive the optical test output signal and generate a further electrical signal, the optical test circuit further including a further electrical output for outputting said further electrical signal.

5. A wafer, comprising:
a plurality of integrated circuits separated by a scribe line;
a testing circuit;
wherein said testing circuit comprises an optical test circuit having:
an optical input located within the scribe line and configured to receive an optical test signal;
a test channel located within the scribe line and configured to receive said optical test signal and produce an optical test output signal in response to processing of the optical test signal through at least one optical device under test circuit;
a photodetector located within the scribe line and coupled to receive said optical test output signal and generate an electrical signal; and
an electrical output for outputting said electrical signal.

6. The wafer of claim 5 , wherein the at least one optical device under test circuit comprises a plurality of series coupled optical device under test circuits located within the scribe line.

7. The wafer of claim 5 , wherein the test channel comprises a further photodetector located within the scribe line and coupled to receive the optical test signal and generate a further electrical signal, the optical test circuit further including a further electrical output for outputting said further electrical signal.

8. The wafer of claim 5 , wherein the test channel comprises a further photodetector located within the scribe line and coupled to receive the optical test output signal and generate a further electrical signal, the optical test circuit further including a further electrical output for outputting said further electrical signal.

Assignees

• St Microelectronics Crolles 2 Sas

Inventors

• Grosse Philippe
• Le Maitre Patrick
• Carpentier Jean-Francois

Classifications

• G01M11/02 Primary

  Testing optical properties · CPC title

• G02B6/00

  Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings · CPC title

• G01R31/311

  of integrated circuits {(G01R31/31728 takes precedence)} · CPC title

• G02B6/34

  utilising prism or grating {(G02B6/293 takes precedence)} · CPC title

• G01M11/33 Primary

  with a light emitter being disposed at one fibre or waveguide end-face, and a light receiver at the other end-face · CPC title