Display substrate, method of manufacturing display substrate, and display device including display substrate

Patent metadata

Field	Value
Publication number	US-11678528-B2
Application number	US-202016953188-A
Country	US
Kind code	B2
Filing date	Nov 19, 2020
Priority date	Nov 26, 2018
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

A method of manufacturing a display substrate may include the following steps: forming a drain electrode on a pixel area of a substrate; forming a pad electrode on a pad area of the substrate; forming an inorganic insulation layer that covers the drain electrode and the pad electrode; forming an organic insulation member that has a first thickness at the pixel area of the substrate, has a second thickness less than the first thickness at the pad area of the substrate, exposes a first portion of the inorganic insulation layer on the drain electrode, and exposes a second portion of the inorganic insulation layer on the pad electrode; removing the first portion of the inorganic insulation layer and the second portion of the inorganic insulation layer; and partially removing the organic insulation member.

First claim

What is claimed is:

1. A display substrate, comprising:
a substrate including a pixel area and a pad area;
a semiconductor member overlapping the pixel area of the substrate;
a gate electrode overlapping the semiconductor member;
a source electrode and a drain electrode directly contacting the semiconductor member;
a pad electrode overlapping the pad area of the substrate;
a passivation layer at least partially covering each of the source electrode, the drain electrode, and the pad electrode, the passivation layer including a first contact hole that partially exposes the drain electrode and including a second contact hole that partially exposes the pad electrode;
a first planarization layer disposed on the passivation layer, overlapping the pixel area of the substrate, and including a third contact hole that corresponds to the first contact hole, wherein a face of the passivation layer is spaced from the drain electrode and is exposed by the third contact hole;
a pixel electrode disposed on the first planarization layer, overlapping the pixel area of the substrate, and directly contacting the drain electrode through the first contact hole and the third contact hole; and
a second planarization layer disposed on the passivation layer, having a planarized surface spaced apart from the passivation layer, overlapping the pad area of the substrate, and including a fourth contact hole that corresponds to the second contact hole, wherein a maximum thickness of the second planarization layer in a direction perpendicular to the substrate is less than a maximum thickness of the first planarization layer in a direction perpendicular to the substrate.

2. The display substrate of claim 1 , further comprising an insulation interlayer, wherein the source electrode, the drain electrode, and the pad electrode are disposed directly on a same face of the insulation interlayer.

3. The display substrate of claim 1 , wherein the pad electrode includes an intermediate layer including aluminum (Al) and includes two conductive layers respectively disposed on two opposite surfaces of the intermediate layer.

4. The display substrate of claim 3 , wherein the passivation layer covers a side surface of the intermediate layer of the pad electrode.

5. The display substrate of claim 1 , wherein the passivation layer includes silicon nitride.

6. The display substrate of claim 1 , wherein the passivation layer covers a side surface of the pad electrode.

7. The display substrate of claim 1 , wherein a maximum width of the third contact hole in a direction parallel to the substrate is greater than a maximum width of the first contact hole in the direction parallel to the substrate.

8. The display substrate of claim 1 , wherein the first planarization layer and the second planarization layer include a same material.

9. The display substrate of claim 1 , wherein the semiconductor member overlaps a face of the substrate, and wherein the face of the passivation layer is parallel to the face of the substrate.

10. The display substrate of claim 9 , wherein a face of the pixel electrode is parallel to the face of the passivation layer and directly contacts the face of the passivation layer.

11. A display device, comprising:
a substrate including a pixel area and a pad area;
a semiconductor member overlapping the pixel area of the substrate;
a gate electrode overlapping the semiconductor member;
a source electrode and a drain electrode directly contacting the semiconductor member;
a pad electrode overlapping the pad area of the substrate;
a passivation layer at least covering each of the source electrode, the drain electrode, and the pad electrode, the passivation layer including a first contact hole that partially exposes the drain electrode and including a second contact hole that partially exposes the pad electrode;
a first planarization layer disposed on the passivation layer, overlapping the pixel area of the substrate, and including a third contact hole that corresponds to the first contact hole, wherein a face of the passivation layer is spaced from the drain electrode and is exposed by the third contact hole;
a second planarization layer disposed on the passivation layer, having a planarized surface spaced apart from the passivation layer, overlapping the pad area of the substrate, and including a fourth contact hole that corresponds to the second contact hole, wherein a maximum thickness of the second planarization layer in a direction perpendicular to the substrate is less than a maximum thickness of the first planarization layer in a direction perpendicular to the substrate;
a pixel electrode disposed on the first planarization layer, overlapping the pixel area of the substrate, and directly contacting the drain electrode through the first contact hole and the third contact hole;
an emission layer disposed on the pixel electrode; and
an opposite electrode disposed on the emission layer.

12. The display device of claim 11 , wherein the semiconductor member overlaps a face of the substrate, and wherein the face of the passivation layer is parallel to the face of the substrate.

13. The display device of claim 12 , wherein a face of the pixel electrode is parallel to the face of the passivation layer and directly contacts the face of the passivation layer.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Sang Gab
• Cho Hyunmin
• Kim Taesung
• Bae Subin
• Jeong Yu-Gwang
• Kim Jinseock

Classifications

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K59/124 Primary

  Insulating layers formed between TFT elements and OLED elements · CPC title

• H10K50/818

  Reflective anodes, e.g. ITO combined with thick metallic layers · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K71/233

  by photolithographic etching · CPC title