Method of reducing program disturbance in memory device and memory device utilizing same

Patent metadata

Field	Value
Publication number	US-11676646-B2
Application number	US-202117539133-A
Country	US
Kind code	B2
Filing date	Nov 30, 2021
Priority date	Dec 9, 2019
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

A memory device includes bit lines, and a cell array including strings, each of which includes memory cells, a select cell coupled to a respective one of the bit lines, and a dummy cell between the select cell and the memory cells. The memory device also includes a select line coupled to the select cells, a dummy word line coupled to the dummy cells, word lines each coupled to a respective row of the memory cells, and a controller coupled to the cell array. The controller is configured to drive a voltage on the dummy word line from a first level to a second level lower than the first level. The controller is also configured to drive a voltage on the select line from the first level to the second level, such that the voltage on the select line reaches the second level after the voltage on the dummy word line reaches the second level. The controller is further configured to, after the voltage on the select line reaches the second level, drive a voltage on a selected word line of the word lines from the second level to a third level higher than the first level to program the memory cells coupled to the selected word line.

First claim

What is claimed is:

1. A method for operating a memory device, the memory device comprising bit lines, a cell array comprising strings, each of the strings comprising memory cells, a select cell coupled to a respective one of the bit lines, and a dummy cell between the select cell and the memory cells, a select line coupled to the select cells, a dummy word line coupled to the dummy cells, and word lines each coupled to a respective row of the memory cells, the method comprising:
driving a voltage on the dummy word line from a first level to a second level lower than the first level;
after driving the voltage on the dummy word line from the first level to the second level, driving a voltage on the select line from the first level to the second level, the voltage on the select line arriving at the second level after the voltage on the dummy word line reaches the second level; and
after the voltage on the select line reaches the second level, driving a voltage on a selected word line of the word lines from the second level to a third level higher than the first level to program the memory cells coupled to the selected word line.

2. The method of claim 1 , further comprising driving an unselected bit line of the bit lines coupled to a program inhibited string of the strings from the first level to the second level, the voltage on the unselected bit line arriving at the second level after the voltage on the select line reaches the second level.

3. The method of claim 2 , further comprising driving the voltage on the selected word line from the second level to the third level after the voltage on the unselected bit line reaches the second level.

4. The method of claim 2 , further comprising simultaneously driving the voltages on the dummy word line, the select line, and the unselected bit line from the second level to the first level before driving the voltage on the dummy word line from the first level to the second level.

5. The method of claim 1 , further comprising driving the voltage on the dummy word line from the second level to a fourth level higher than the first level when driving the voltage on the selected word line from the second level to the third level.

6. The method of claim 5 , wherein the fourth level is lower than the third level.

7. The method of claim 1 , further comprising driving a voltage on an unselected word line of the word lines from the second level to a fifth level lower than the third level when driving the voltage on the selected word line from the second level to the third level.

8. The method of claim 1 , wherein the second level is ground.

9. The method of claim 1 , further comprising:
before driving the voltage on the selected word line of the word lines from the second level to the third level, maintaining a voltage on each of the word lines at the second level.

10. A method for operating a memory device comprising a cell array that comprises a memory string coupled to a bit line, the memory string comprising memory cells each coupled to a word line, a select cell coupled to a select line, and a dummy cell coupled to a dummy word line and arranged between the select cell and the memory cells, the method comprising before performing a program operation on a target memory cell:
retaining an on-state of the select cell and applying a voltage to the dummy word line to turn off the dummy cell, the bit line being an unselected bit line in the program operation on the target memory cell; and
after applying the voltage to the dummy word line, applying a same voltage to the select line to turn off the select cell.

11. The method of claim 10 , wherein:
the voltage is a first voltage; and
retaining the on-state of the select cell comprises maintaining a second voltage on the select line coupled to the select cell.

12. The method of claim 10 , wherein:
the voltage is a first voltage; and
the method further comprises after applying the first voltage to the select line, applying a third voltage to a selected word line coupled to the target memory cell to perform the program operation on the target memory cell.

13. The method of claim 12 , further comprising:
before applying the third voltage to the selected word line, driving a voltage on the selected word line to a sixth voltage, the sixth voltage being less than the third voltage.

14. The method of claim 12 , further comprising:
when applying the third voltage to the selected word line, applying a fourth voltage to the dummy word line, the fourth voltage being lower than the third voltage.

15. The method of claim 14 , further comprising:
when applying the third voltage to the selected word line, applying a fifth voltage to an unselected word line, the unselected word line being a word line of the word lines other than the selected word line, and the fifth voltage being lower than the third voltage.

16. The method of claim 15 , wherein:
the fourth voltage is equal to the fifth voltage.

17. The method of claim 10 , further comprising:
after applying the voltage to the select line, applying a same voltage to the bit line.

18. The method of claim 17 , wherein:
the voltage is a first voltage; and
the method further comprises after applying the first voltage to the bit line, applying a third voltage to a selected word line coupled to the target memory cell to perform the program operation on the target memory cell.

19. The method of claim 10 , wherein:
the voltage is a first voltage; and
the method further comprises before applying the first voltage to the dummy word line, simultaneously applying a second voltage to the dummy word line and the select line to turn on the dummy cell and the select cell, respectively, the second voltage being higher than the first voltage.

20. The method of claim 10 , wherein:
the voltage is a ground voltage.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Li Shan
• You Kaikai
• Cui Ying
• Jia Jianquan
• Li Kaiwei
• Zhang An

Classifications

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C8/08 Primary

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C7/14

  Dummy cell management; Sense reference voltage generators · CPC title

• G11C16/3418 Primary

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title