Memory for implementing at least one of reading or writing command

Patent metadata

Field	Value
Publication number	US-11676642-B2
Application number	US-202117405107-A
Country	US
Kind code	B2
Filing date	Aug 18, 2021
Priority date	Aug 21, 2020
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

A memory, comprising: a plurality of storage groups, first signal lines and second signal lines. The plurality of storage groups is arranged along a first direction, each one of the storage groups includes multiple banks, which are arranged along a second direction, and the first direction is perpendicular to the second direction; the first signal lines extend along the first direction, each first signal line is arranged correspondingly to more than one of the multiple banks, and configured to transmit storage data of the more than one of the multiple banks; and the second signal lines extend along the first direction, each one of the second signal lines is arranged correspondingly to a respective bank, and configured to transmit the storage data of the respective bank; wherein the first signal lines exchange the storage data with the second signal lines through respective data exchange circuits.

First claim

The invention claimed is:

1. A memory, comprising:
a plurality of storage groups, wherein the plurality of storage groups are arranged along a first direction, each one of the plurality of storage groups comprises a plurality of banks, the plurality of banks are arranged along a second direction, and the first direction is perpendicular to the second direction;
first signal lines extending along the first direction; wherein each one of the first signal lines is arranged correspondingly to more than one of the plurality of banks and is configured to transmit storage data of the more than one of the plurality of banks;
second signal lines extending along the first direction, each one of the second signal lines being arranged correspondingly to a respective bank and configured to transmit storage data of the respective bank;
wherein the first signal lines exchange the storage data with the second signal lines through respective data exchange circuits; and
power lines and grounding lines, wherein the power lines or the grounding lines are arranged at two sides of the first signal lines, and the power lines or the grounding lines are arranged at two sides of the second signal lines.

2. The memory of claim 1 , wherein the first signal lines comprise a plurality of first metal lines with a same line width, and the second signal lines comprise a plurality of second metal lines with a same line width.

3. The memory of claim 2 , wherein the plurality of first metal lines have a line width less than a line width of the plurality of second metal lines.

4. The memory of claim 2 , wherein a distance between two of the plurality of first metal lines is greater than a distance between two of the plurality of second metal lines.

5. The memory of claim 1 , wherein the memory further comprises a top metal layer; and the first signal lines, the second signal lines, the power lines and the grounding lines are arranged in the top metal layer.

6. The memory of claim 5 , wherein the memory further comprises a sub-top metal layer, wherein the power lines or the grounding lines are also arranged in the sub-top metal layer, and the power lines or the grounding lines are arranged along the first direction and the second direction in the sub-top metal layer.

7. The memory of claim 6 , wherein in the sub-top metal layer, the power lines or the grounding lines arranged along the second direction are located right above the plurality of storage groups, and located in middle and two edges parallel to the second direction of the plurality of storage groups.

8. The memory of claim 7 , wherein each one of the power lines arranged along the first direction is located between corresponding power lines arranged along the second direction, or each one of the grounding lines arranged along the first direction is located between corresponding grounding lines arranged along the second direction.

9. The memory of claim 1 , wherein the memory further comprises a channel data bus, which exchanges the storage data with the first signal lines through the data exchange circuits.

10. The memory of claim 9 , wherein the channel data bus is arranged away from one side of the plurality of storage groups.

11. The memory of claim 1 , wherein a number of the plurality of storage groups is n, a number of the second signal lines is m times of a number of the first signal lines, and m and n are positive integers.

12. A memory, comprising:
a plurality of storage groups, wherein the plurality of storage groups are arranged along a first direction, each one of the plurality of storage groups comprises a plurality of banks, the plurality of banks are arranged along a second direction, and the first direction is perpendicular to the second direction;
first signal lines extending along the first direction; wherein each one of the first signal lines is arranged correspondingly to more than one of the plurality of banks and is configured to transmit storage data of the more than one of the plurality of banks;
second signal lines extending along the first direction, each one of the second signal lines being arranged correspondingly to a respective bank and configured to transmit storage data of the respective bank;
wherein the first signal lines exchange the storage data with the second signal lines through respective data exchange circuits;
the first signal lines comprise a plurality of first metal lines with a same line width, and the second signal lines comprise a plurality of second metal lines with a same line width; and
the plurality of first metal lines have a line width less than a line width of the plurality of second metal lines.

Assignees

• Changxin Memory Tech Inc

Inventors

• Shang Weibing
• Zhang Fengqin
• Ji Kangling
• Tian Kai
• Wu Xianjun

Classifications

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G11C5/06 Primary

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G11C5/14

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title