Accessing primitive data using tessellated primitive ID

Patent metadata

Field	Value
Publication number	US-11676336-B2
Application number	US-202217707032-A
Country	US
Kind code	B2
Filing date	Mar 29, 2022
Priority date	Apr 5, 2018
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

A method of generating identifiers (IDs) for primitives and optionally vertices during tessellation. The IDs include a binary sequence of bits that represents the sub-division steps taken during the tessellation process and so encodes the way in which tessellation has been performed. Such an ID may subsequently be used to generate a random primitive or vertex and hence recalculate vertex data for that primitive or vertex.

First claim

What is claimed is:

1. A method of performing tessellation in a computer graphics system, the method comprising:
receiving an ID of a primitive in a tessellation unit;
truncating the ID of the received primitive to generate vertex IDs of vertices in the primitive;
using the vertex IDs to calculate UV coordinates for each vertex in the primitive and for parent vertices for a sub-set of the vertices in the primitive; and
using the calculated UV coordinates to generate vertex data for each vertex in the primitive.

2. The method according to claim 1 , wherein the ID of a primitive comprises a sequence of bits describing a sub-division sequence used to generate the primitive.

3. The method according to claim 1 , wherein the ID of a primitive comprises a sequence of bits that specifies a recursive sequence taken during a tessellation process.

4. The method according to claim 3 , wherein the recursive sequence defines a subdivision hierarchy and truncating the ID of the primitive to generate vertex IDs of the vertices in the primitive comprises:
performing a first truncation according to a first function that steps one step back up the subdivision hierarchy to generate a first vertex ID;
performing two further truncations according to a second function to generate second and third vertex IDs, wherein the second function steps two steps back up the subdivision hierarchy to generate the second vertex ID and steps S steps back up the subdivision hierarchy to generate the third vertex ID, wherein a value of S is determined by the ID of the primitive.

5. The method according to claim 4 , wherein the recursive sequence defines a subdivision hierarchy, and wherein the method further comprises for the sub-set of the vertices in the primitive, truncating the vertex ID of the vertex in a plurality of different places to generate IDs of parent vertices by:
for the sub-set of the vertices in the primitive, performing two truncations according to the second function to generate a first parent vertex ID and a second parent vertex ID, wherein the second function steps two steps back up the subdivision hierarchy to generate the first parent vertex ID and steps S steps back up the subdivision hierarchy to generate the second parent vertex ID, wherein a value of S is determined by the vertex ID.

6. The method according to claim 4 , wherein the recursive sequence defines a subdivision hierarchy and using the vertex IDs to calculate UV coordinates for each vertex in the primitive and the parent vertices for the sub-set of vertices in the primitive, comprises:
for each vertex in the primitive: using a third function to calculate a vertex UV coordinate for the vertex from the vertex ID; and
for the sub-set of the vertices in the primitive: using the third function to calculate vertex UV coordinates for the parent vertices of the vertex from the vertex IDs of the parent vertices.

7. The method according to claim 6 , wherein the third function comprises:
generating a fixed complex value;
forming a sequence of scaled versions of the complex value for each bit of a vertex ID;
summing all the scaled versions in the sequence; and
performing a scaling and translation operation to generate the vertex UV coordinates corresponding to the vertex ID.

8. The method according to claim 3 , wherein each vertex has an associated displacement factor and the sub-set comprises only those vertices in the primitive with a displacement factor that is not equal to a maximum value of displacement factor.

9. A computer graphics system comprising:
a tessellation unit comprising hardware logic arranged to:
receive an ID of a primitive;
truncate the ID of the primitive to generate vertex IDs of vertices in the primitive; and
use the vertex IDs to calculate UV coordinates for each vertex in the primitive and for parent vertices for a sub-set of the vertices in the primitive; and

hardware logic arranged to use the calculated UV coordinates to generate vertex data for each vertex in the primitive.

10. The computer graphics system according to claim 9 , wherein the ID of a primitive comprises a sequence of bits describing a sub-division sequence used to generate the primitive.

11. The computer graphics system according to claim 9 , wherein the ID of a primitive comprises a sequence of bits that specifies a recursive sequence taken during a tessellation process.

12. The computer graphics system according to claim 11 , wherein the recursive sequence defines a subdivision hierarchy and wherein the hardware logic that is arranged to truncate the ID of the primitive to generate vertex IDs of the vertices in the primitive is in a tessellation unit and comprises hardware logic arranged to:
perform a first truncation according to a first function that steps one step back up the subdivision hierarchy to generate a first vertex ID;
perform two further truncations according to a second function to generate second and third vertex IDs, wherein the second function steps two steps back up the subdivision hierarchy to generate the second vertex ID and steps S steps back up the subdivision hierarchy to generate the third vertex ID, wherein a value of S is determined by the ID of the primitive.

13. The computer graphics system according to claim 12 , wherein the recursive sequence defines a subdivision hierarchy and for the sub-set of the vertices in the primitive, and wherein the hardware logic is in a tessellation unit, is further arranged to truncate the vertex ID of the vertex in a plurality of different places to generate IDs of parent vertices and comprises hardware logic arranged:
for the sub-set of the vertices in the primitive, to perform two truncations according to the second function to generate a first parent vertex ID and a second parent vertex ID, wherein the second function steps two steps back up the subdivision hierarchy to generate the first parent vertex ID and steps S steps back up the subdivision hierarchy to generate the second parent vertex ID, wherein a value of S is determined by the vertex ID.

14. The computer graphics system according to claim 12 , wherein the recursive sequence defines a subdivision hierarchy and the hardware logic arranged to use the vertex IDs to calculate UV coordinates for each vertex in the primitive and the parent vertices for the sub-set of vertices in the primitive is in a tessellation unit and comprises hardware logic arranged:
for each vertex in the primitive: to use a third function to calculate a vertex UV coordinate for the vertex from the vertex ID; and
for the sub-set of the vertices in the primitive: to use the third function to calculate vertex UV coordinates for the parent vertices of the vertex from the vertex IDs of the parent vertices.

15. The computer graphics system according to claim 14 , wherein the third function comprises:
generating a fixed complex value;
forming a sequence of scaled versions of the complex value for each bit of a vertex ID;
summing all the scaled versions in the sequence; and
performing a scaling and translation operation to generate the vertex UV coordinates corresponding to the vertex ID.

16. The computer graphics system according to claim 15 , wherein the system is embodied in hardware on an integrated circuit.

17. The computer graphics system according to claim 11 , wherein each vertex has an associated displacement factor and the sub-set comprises only those vertices in the primitive with a displacement factor that is not equal to a maximum value of displacement factor.

18. A non-transitory computer-reada

Assignees

• Imagination Tech Ltd

Inventors

• Lacey Peter Malcolm

Classifications

• G06T17/005

  Tree description, e.g. octree, quadtree · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title

• G06T19/20 Primary

  Editing of three-dimensional [3D] images, e.g. changing shapes or colours, aligning objects or positioning parts · CPC title

• G06T2200/28

  involving image processing hardware · CPC title

• G06T17/20 Primary

  Finite element generation, e.g. wire-frame surface description, {tesselation} · CPC title