Graphics library extensions

Patent metadata

Field	Value
Publication number	US-11676321-B2
Application number	US-202016915340-A
Country	US
Kind code	B2
Filing date	Jun 29, 2020
Priority date	Jun 8, 2012
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

A method and system for performing graphics processing is provided. The method and system includes storing stencil buffer values in a stencil buffer; generating either or both of a reference value and a source value in a fragment shader; comparing the stencil buffer values against the reference value; and processing a fragment based on the comparing the stencil buffer values against the reference value.

First claim

What is claimed is:

1. A method for graphics processing, comprising:
storing stencil buffer values in a stencil buffer;
generating a reference value in a fragment shader;
comparing the stencil buffer values against the reference value generated by
processing a fragment based on the comparing; and
operating on the stencil buffer values based on a combination of the stored stencil buffer values, the reference value, and the source value, the operating including modifying the stencil buffer based on one of the reference value or the source value using an operation selection value that selects one of the source value and the reference value for the operating,
wherein the operating includes any one or a combination of: keeping a stencil buffer value; setting a stencil buffer value to zero; setting a stencil buffer value to a maximum representable value; replacing a stencil buffer value with the reference value; replacing a stencil buffer value with the source value; incrementing a stencil buffer value by the source value with saturation; decrementing a stencil buffer value by the source value with saturation; bitwise inverting a stencil buffer value; incrementing a stencil buffer value by the source value without saturation such that decrementing the stencil buffer value causes a result of the operation to be masked by a number of bits representable by the stencil buffer; decrementing a stencil buffer value by the source value without saturation; logically ANDing a stencil buffer value and the source value; logically XORing a stencil buffer value and the source value; logically ORing a stencil buffer value and the source value; logically NORing a stencil buffer value and the source value; logically XORing a stencil buffer value and the source value; and replacing a stencil buffer value with a logically inverted result of logically XORing a stencil buffer value and the source value; and logically NANDing a stencil buffer value and the source value.

2. The method of claim 1 , wherein incrementing and decrementing with saturation clamps the stencil buffer value between 0 and the maximum representable value.

3. The method of claim 1 , wherein decrementing without saturation is performed such that decrementing the stencil buffer value causes the result of the operation to be masked by a number of bits representable by the stencil buffer.

4. The method of claim 1 , wherein the stencil buffer values are unsigned integers.

5. The method of claim 1 , wherein the processing includes discarding the fragment.

6. A system, comprising:
a stencil buffer configured to store stencil buffer values; and
a processor configured to:
generate a reference value in a fragment shader;
compare the stencil buffer values against the reference value generated by the fragment shader or a source value supplied by an application;
process a fragment based on the comparing; and
operate on the stencil buffer values based on a combination of the stored stencil buffer values, the reference value, and the source value, the operating including modifying the stencil buffer based on one of the reference value or the source value using an operation selection value that selects one of the source value and the reference value for the operating,
wherein the operating includes any one or a combination of the following operations: keeping a stencil buffer value; setting a stencil buffer value to zero; setting a stencil buffer value to a maximum representable value; replacing a stencil buffer value with the reference value; replacing a stencil buffer value with the source value; incrementing a stencil buffer value by the source value with saturation; decrementing a stencil buffer value by the source value with saturation; bitwise inverting a stencil buffer value; incrementing a stencil buffer value by the source value without saturation such that incrementing the stencil buffer value causes a result of the operation to be masked by a number of bits representable by the stencil buffer; decrementing a stencil buffer value by the source value without saturation such that decrementing the stencil buffer value causes the result of the operation to be masked by a number of bits representable by the stencil buffer; logically ANDing a stencil buffer value and the source value; logically XORing a stencil buffer value and the source value; logically ORing a stencil buffer value and the source value; logically NORing a stencil buffer value and the source value; logically XORing a stencil buffer value and the source value; and replacing a stencil buffer value with a logically inverted result of logically XORing a stencil buffer value and the source value; and logically NANDing a stencil buffer value and the source value.

7. The system of claim 6 , wherein incrementing and decrementing with saturation clamps the stencil buffer value between 0 and the maximum representable value.

8. The system of claim 6 , wherein decrementing without saturation is performed such that decrementing the stencil buffer value causes the result of the operation to be masked by a number of bits representable by the stencil buffer.

9. The system of claim 6 , wherein the stencil buffer values are unsigned integers.

10. The system of claim 6 , wherein the processing includes discarding the fragment.

Assignees

• Advanced Micro Devices Inc

Inventors

• Sellers Graham
• Zolnowski Eric
• Boudier Pierre
• Obert Juraj

Classifications

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T15/80

  Shading · CPC title

• G06T15/04

  Texture mapping · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title

• G06T11/40

  Filling planar surfaces by adding surface attributes, e.g. adding colours or textures · CPC title