Process identifier transition monitoring and assessment

Patent metadata

Field	Value
Publication number	US-11675897-B2
Application number	US-202117523748-A
Country	US
Kind code	B2
Filing date	Nov 10, 2021
Priority date	May 11, 2018
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

A process identifier transition monitor captures and assesses activities associated with a microprocessor or a microcontroller. Monitoring and assessment is performed by detection of process identifier transitions, which may be driven by an occurrence of one or more activities, such as execution of application software, system hardware mechanisms, or processor-internal mechanisms. Process identifier transitions are assessed to determine whether such transitions were expected. If a detected process identifier transition was not expected, then a system alert may be transmitted or some other appropriate response taken within the system.

First claim

What is claimed is:

1. A vehicle system, comprising:
a first memory configured to store a process identifier;
a vehicle system controller configured to control an operation of a vehicle;
a hardware peripheral device in electrical communication with the first memory, the hardware peripheral device including a processor configured to execute:
a first process associated with a first function of the hardware peripheral device, wherein the first process is associated with an idle state of the hardware peripheral device and the first process is associated with a first process identifier, and
a second process associated with a second function of the hardware peripheral device, wherein the second process is associated with a reset state of the hardware peripheral device and the second process is associated with a second process identifier, and wherein the processor is configured to store the first process identifier into the first memory when the processor is executing the first process and store the second process identifier into the first memory when the processor is executing the second process;

a second memory configured to store a process transition permission matrix including a plurality of process identifier transitions, wherein each process identifier transition in the plurality of process identifier transitions includes a pair of process identifiers, and an indication for each process identifier transition in the plurality of process identifier transitions, of whether the process identifier transition is authorized; and
a process transition monitor in electrical communication with the first memory and the second memory, the process transition monitor being configured to:
periodically monitor the process identifier stored in the first memory, and upon determining the process identifier stored in the first memory has transitioned from the first process identifier to the second process identifier:
access the process transition permission matrix to identify a first process identifier transition that includes the first process identifier and the second process identifier,
determine, based on the indication of whether the first process identifier transition is authorized, that the first process identifier transition is not authorized, and
upon determining that the first process identifier transition is not authorized, cause the vehicle system controller to shut down a drive train of the vehicle.

2. The vehicle system of claim 1 , wherein the process transition monitor is configured to, upon determining that the first process identifier transition is not authorized, cause the vehicle system controller to generate an output using a user interface of the vehicle, wherein the output indicates an error has occurred in the vehicle.

3. The vehicle system of claim 2 , wherein the output includes a check-engine light.

4. The vehicle system of claim 1 , wherein the process transition monitor is configured to, upon determining that the first process identifier transition is not authorized, initiate a reset of the hardware peripheral device.

5. A system, comprising:
a first memory configured to store a process identifier;
a hardware peripheral device in electrical communication with the first memory, the hardware peripheral device including a processor configured to execute:
a first process associated with a first function of the hardware peripheral device, wherein the first process is associated with a first process identifier, and
a second process associated with a second function of the hardware peripheral device, wherein the second process associated with a second process identifier, and wherein the processor is configured to store the first process identifier into the first memory when the processor is executing the first process and store the second process identifier into the first memory when the processor is executing the second process;

a second memory configured to store a process transition permission matrix including a plurality of process identifier transitions and identifies for each process identifier transition an indication of whether the process identifier transition is authorized; and
a process transition monitor in electrical communication with the first memory and the second memory, the process transition monitor being configured to:
determine the process identifier stored in the first memory has transitioned from the first process identifier to the second process identifier in a first process identifier transition,
access the process transition permission matrix to determine that the transition from the first process identifier to the second process identifier is not authorized, and
execute a response as a function of the transition from the first process identifier to the second process identifier not being authorized.

6. The system of claim 5 , further comprising a third memory configured to store a response matrix that includes the plurality of process identifier transitions and identifies for each process identifier transition a predetermined response.

7. The system of claim 6 , wherein the process transition monitor is configured to determine the response by identifying in the response matrix a first predetermined response associated with the first process identifier transition.

8. The system of claim 7 , wherein the first predetermined response includes a functional reset configured to reset the hardware peripheral device or a destructive reset configured to reset the system.

9. The system of claim 7 , wherein the first predetermined response includes transmitting a signal to a vehicle system controller to cause the vehicle system controller to execute a specified function in response to the signal.

10. The system of claim 9 , wherein the specified function includes shutting down a drive train of a vehicle.

11. A system, comprising:
a first memory configured to store a process identifier;
a second memory configured to store a response matrix that includes a plurality of process identifier transitions and identifies a predetermined response for each process identifier transition of the plurality of process identifier transitions;
a processor configured to execute:
a first process associated with a first process identifier, and
a second process associated with a second process identifier, and wherein the processor is configured to store the first process identifier into the first memory following execution of the first process and store the second process identifier into the first memory following execution of the second process; and
a process transition monitor in electrical communication with the first memory, the process transition monitor being configured to:
retrieve, at a first time, the first process identifier from the first memory,
receive, at a second time after the first time, the second process identifier from the first memory,
determine a transition from the first process identifier to the second process identifier is an unauthorized process identifier transition, and
execute a response as a function of the transition from the first process identifier to the second process identifier being the unauthorized process identifier transition.

12. The system of claim 11 , wherein the process transition monitor is configured to determine the response by identifying in the response matrix a first predetermined response associated with the transition from the first process identifier to the second process identifier.

13. The system of claim 12 , wherein the first predetermined response includes a functional reset configured to reset the processor or a destructive reset configured to reset the system.

Assignees

• Nxp Usa Inc

Inventors

• Regner Markus
• Ebert Florian Frank
• Seibold Peter

Classifications

• G06F21/554

  involving event detection and direct action · CPC title

• G06F11/3409

  for performance assessment · CPC title

• G06F11/0721

  within a central processing unit [CPU] · CPC title

• G06F21/52 Primary

  during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title