Enhanced low-priority arbitration

Patent metadata

Field	Value
Publication number	US-11675718-B2
Application number	US-202117214771-A
Country	US
Kind code	B2
Filing date	Mar 26, 2021
Priority date	Mar 26, 2021
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

A computing system may implement a low priority arbitration interrupt method that includes receiving a message signaled interrupt (MSI) message from an input output hub (I/O hub) transmitted over an interconnect fabric, selecting a processor to interrupt from a cluster of processors based on arbitration parameters, and communicating an interrupt service routine to the selected processor, wherein the I/O hub and the cluster of processors are located within a common domain.

First claim

What is claimed is:

1. A priority arbitration interrupt method, comprising:
receiving an interrupt request from an input output hub (I/O hub) transmitted over an interconnect fabric;
in response to receiving the interrupt request, selecting a processor to interrupt from a cluster of processors based on the processor residing in a common domain with the I/O hub; and
communicating an interrupt routine to the selected processor.

2. The method of claim 1 , wherein the selecting the processor is based on arbitration parameters and further comprises selecting a focus processor that is processing or scheduled to process a same interrupt vector for another interrupt as for the received interrupt request.

3. The method of claim 1 , further comprising excluding one or more processors from the selecting of the processor to service the interrupt from the cluster of processors based on a power state of the one or more processors.

4. The method of claim 1 , wherein the selecting the processor is based on arbitration parameters and further comprises selecting a prior focus processor that has previously processed a same interrupt vector for another interrupt as for the received interrupt request.

5. The method of claim 4 , further comprising:
if the prior focus processor has an arbitration priority register (APR) value higher than a threshold value, reading the APR value for each processor of the cluster of processors;
if at least one processor of the cluster of processors has a zero APR value, selecting the processor having the zero APR value; and
if no processors of the cluster of processors have a zero APR value, selecting a last processor with a lowest APR value.

6. The method of claim 1 , wherein the selecting the processor is based on arbitration parameters and further comprises selecting a processor in a same cache domain as a prior focus processor that has previously processed a same interrupt vector for another interrupt request as for the received interrupt request.

7. The method of claim 1 , wherein the selecting the processor is based on arbitration parameters and further comprises selecting a processor based on an arbitration priority register (APR) value.

8. The method of claim 1 , further comprising omitting one or more processors from the selecting based on the one or more processors having a lower power state than one or more other processors in the cluster of processors.

9. A programmable interrupt controller (PIC), comprising:
an input configured to receive over an interconnect fabric an interrupt request from a device coupled to an input output hub (I/O hub); and
PIC logic configured to:
in response to receiving the interrupt request, select a processor to interrupt from a cluster of processors based on the processor residing in a same domain as the I/O hub and PIC, and
communicate an interrupt service routine to the selected processor.

10. The programmable interrupt controller of claim 9 , wherein the PIC logic is further configured to select the processor based on arbitration parameters by selecting a focus processor that is processing or scheduled to process a same interrupt vector for another interrupt message as for the interrupt request.

11. The programmable interrupt controller of claim 9 , wherein the PIC logic is further configured to, when selecting the processor to interrupt, exclude one or more processors of the cluster of processors from selection based on a power state of the one or more processors.

12. The programmable interrupt controller of claim 9 , wherein the PIC logic is further configured to select the processor based on arbitration parameters by selecting a prior focus processor that has previously processed a same interrupt vector for another interrupt message as for the interrupt request.

13. The programmable interrupt controller of claim 12 , wherein the PIC logic is further configured to:
if the prior focus processor has an arbitration priority register (APR) value higher than a threshold value, select the processor from one or more processors that have a zero APR value if at least one of the one or more processors has a zero APR value, and
select a last processor with a lowest APR value if none of the one or more processors have a zero APR value.

14. The programmable interrupt controller of claim 9 , wherein the PIC logic is configured to select the processor based on arbitration parameters by selecting a processor in a same cache domain as a prior focus processor that has previously processed a same interrupt vector for another interrupt message as for the interrupt request.

15. The programmable interrupt controller of claim 9 , wherein the PIC logic is further configured to select the processor based on arbitration parameters by selecting a processor based on an arbitration priority register (APR) value.

16. The programmable interrupt controller of claim 9 , wherein the PIC logic is further configured to omit one or more processors from selection from among the cluster of processors based on the one or more processors having a lower power state than one or more other processors in the cluster of processors.

17. A computing system, comprising:
an interconnect fabric;
a core complex comprising a cluster of processors, the core complex coupled with the interconnect fabric;
a programmable interrupt controller (PIC) coupled to PIC registers comprising arbitration priority registers (APR) and state registers, each APR and state register corresponding to a respective processor of the cluster of processors; and
an input/output hub (I/O hub) coupled to one or more devices and the interconnect fabric, the I/O hub to send an interrupt request from the one or more devices to the PIC over the interconnect fabric, the PIC to select a processor to interrupt from the cluster of processors in the core complex based on the processor residing within a common domain with the I/O hub.

18. The computing system of claim 17 , wherein the PIC is further configured to select the processor based on arbitration parameters by selecting a prior focus processor that has previously processed a same interrupt vector for another interrupt request as for the sent interrupt request.

19. The computing system of claim 18 , wherein the PIC is further configured to, if the prior focus processor has an APR value higher than a threshold value:
select the processor from the cluster of processors that have a zero APR value if at least one processor in the cluster of processors has a zero APR value; and
if none of the cluster of processors have a zero APR value, select a last processor with a lowest APR value.

20. The computing system of claim 18 , wherein the PIC is further configured to select the processor based on arbitration parameters by selecting the processor in a same cache domain as the prior focus processor that has previously processed a same interrupt vector for another interrupt request as for the sent interrupt request.

Assignees

• Advanced Micro Devices Inc

Inventors

• Morton Eric Christopher
• Gupta Pravesh
• Broussard Bryan P
• Ou Li

Classifications

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F9/4831

  with variable priority · CPC title

• G06F9/30101

  Special purpose registers · CPC title

• G06F2213/2412

  Dispatching of interrupt load among interrupt handlers in processor system or interrupt controller · CPC title

• G06F13/26

  with priority control · CPC title