Storage device with division based addressing to support host memory array discovery

Patent metadata

Field	Value
Publication number	US-11675708-B1
Application number	US-202117377754-A
Country	US
Kind code	B1
Filing date	Jul 16, 2021
Priority date	Sep 9, 2014
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

First claim

What is claimed is:

1. A storage device comprising:
flash memory, wherein the flash memory is to have one or more block devices at a hierarchically-superior level, one or more segments within each block device at a hierarchically-intermediate level, and storage locations within each segment at a hierarchically-inferior level; and
circuitry to transmit to a host, responsive to receipt of at least one query from the host, information to identify each block device and each segment; and
circuitry to, for each of incoming data access requests,
derive a first address portion from incoming address information, to identify an addressed block device, and
perform one or more operations to subdivide the incoming address information, to derive a second address portion, to identify an addressed segment within the addressed block device, and to identify an addressed storage location within the addressed segment from a third address portion;

wherein, for at least one of the incoming data access requests, the first address portion of the associated incoming address is to specify a block device identified in response to the at least one query from the host, and the associated second address portion of the incoming address is to specify a segment identified in response to the at least one query from the host.

2. The storage device of claim 1 wherein the circuitry to transmit the information to the host is further to transmit to the host a size of a subdivision of the flash memory that is to be erased at-once, and wherein the storage device further comprises circuitry to receive an erase request from the host, the erase request accompanied by information designating the subdivision of the flash memory, and to control the flash memory so as to physically erase those storage locations corresponding to the designated subdivision.

3. The storage device of claim 1 wherein the segments each comprise a respective, mutually exclusive set of one or more logical erase units, each logical erase unit corresponding to a respective physical erase unit.

4. The storage device of claim 1 wherein:
the incoming data access requests are read requests received from a host;
the storage device can receive write requests from the host, wherein the circuitry is to, for each of incoming write requests, derive a first address portion, a second address portion and, identify an addressed block device from the first address portion and identify an addressed segment within the addressed block device from the second address portion, and the storage device comprises circuitry to issue commands to the flash memory in fulfillment of the write requests;
from each of the incoming write requests, the circuitry is to identify a corresponding logical erase unit from the third address portion and is to identify a physical erase unit which is mapped to the corresponding logical erase unit;
the storage device is to assign an address value in association with fulfillment of each of the write requests, is to identify a physical storage location in which associated write data has been stored and which is associated with the corresponding logical erase unit, and comprises circuitry to transmit information representing each assigned address value to the host; and
for one of the read requests which is directed to data which has been written into the flash memory pursuant to one of the write requests, at least one of the first address portion, the second address portion or third address portion associated with the one of the read requests is dependent on the assigned address value which has been transmitted to the host in association with the data which has been written into the flash memory pursuant to the one of the write requests.

5. The storage device of claim 1 wherein:
the flash memory comprises erase units;
the storage drive further comprises circuitry to detect a failure condition associated with individual ones of the erase units;
the storage device further comprises circuitry to transmit address information to the host corresponding to one or more of the erase units for which the failure condition has been detected.

6. The storage device of claim 1 wherein:
the flash memory comprises physical erase units; and
the circuitry to derive is to perform a division operation on the incoming address information to identify the third address portion, and is to identify an addressed logical erase unit and the addressed storage location from the third address portion, and is to identify one of the physical erase units corresponding to the addressed logical erase unit and an offset within the identified one of the physical erase units in dependence on the addressed storage location.

7. The storage device of claim 6 wherein:
the storage drive further comprises circuitry to detect a failure condition associated with individual ones of the physical erase units;
the storage device further comprises circuitry to remap a correspondence between each logical erase unit and a corresponding first one of the physical erase units, in response to detection of the failure condition for the corresponding first one of the physical erase units, to instead correspond to a second one of the physical erase units, for which the failure condition has not been detected; and
for a situation where the failure condition has been detected for the identified one of the erase units, the addressed storage location is to be applied to identify an offset into the second one of the physical erase units.

8. The storage device of claim 1 wherein:
said circuitry comprises at least one processor; and
the storage device further comprises instructions stored on at least one non-transitory storage medium, said instructions when executed to control the at least one processor so as to operate as special purpose circuitry.

9. The storage device of claim 1 wherein:
the storage device can receive a request from the host to copy host-selected data from one storage location in flash memory to another storage location in the flash memory, and the storage device comprises circuitry to issue commands to the flash memory, in response to the request from the host to copy, to read the host-selected data from a first physical storage location in the flash memory and write the host-selected data to a second physical storage location in the flash memory without sending the data being copied to the host;
the request from the host to copy is to designate destination address information corresponding to the second physical storage location; and
the storage device is to identify, from the destination address information, a destination one of the segments within a destination block device of the one or more block devices.

10. The storage device of claim 9 wherein the storage device is to identify from the destination address information a destination logical erase block and is to select a physical erase block that is already mapped to the destination logical erase block.

11. The storage device of claim 1 wherein the storage device is to store, for each segment that is identified to the host in response to the at least one query, at least one metadata value representing the time since data was programmed into at least one structure that forms a part of the respective segment, wherein each value represents time since data was programmed into the at least one structure.

12. The storage device of claim 11 wherein the storage device further comprises circuitry to:
compare the metadata values representing time since data was programmed to at least one threshold;
upon detection that a specific one of the metadata values has satisfied the one or more thresholds, copy data store

Assignees

• Radian Memory Systems Inc

Inventors

• Lercari Robert
• Chen Alan
• Jadon Mike
• Robertson Craig
• Kuzmin Andrey V

Classifications

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F3/0616

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

• G06F12/109

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title