Storage system and method for using read and write buffers in a memory

Patent metadata

Field	Value
Publication number	US-11675512-B2
Application number	US-202217878253-A
Country	US
Kind code	B2
Filing date	Aug 1, 2022
Priority date	Jan 20, 2021
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer and/or a read buffer. When the storage system uses the SLC blocks as a read buffer, the storage system reads data from multi-level cell (MLC) blocks in the memory and stores the data in the read buffer prior to receiving a read command from a host for the data. When the storage system uses the SLC blocks as a write buffer, the storage system retains certain data in the write buffer while other data is flushed from the write buffer to MLC blocks in the memory.

First claim

What is claimed is:

1. In a storage system comprising a memory, wherein the memory comprises a first set of blocks allocated as a write buffer and a second set of blocks, wherein the first set of blocks has a lower latency than the second set of blocks, a method comprising:
receiving, from a host, data to be stored in the memory;
storing the data in the write buffer;
receiving, from the host, a command to flush the write buffer to the second set of blocks in the memory;
determining whether the data is to be retained in the write buffer despite the command to flush the write buffer; and
in response to determining that the data is to be retained in the write buffer, retaining the data in the write buffer despite the command to flush the write buffer.

2. The method of claim 1 , further comprising:
receiving, from the host, a command to flush the data retained in the write buffer.

3. The method of claim 1 , further comprising:
receiving, from the host, information indicating that the data is to be retained in the write buffer.

4. The method of claim 3 , wherein the information indicates one of a plurality of different retention levels.

5. The method of claim 3 , wherein the information comprises a dedicated command.

6. The method of claim 1 , further comprising:
receiving, from the host, a maximum size of the write buffer.

7. The method of claim 1 , wherein the first set of blocks comprises single-level cell (SLC) blocks and the second set of blocks comprises multi-level cell (MLC) blocks.

8. The method of claim 1 , wherein the first set of blocks comprises XPOINT memory and the second set of blocks comprises flash memory.

9. The method of claim 1 , wherein the memory comprises a three-dimensional memory.

10. A storage system comprising:
a memory comprising a first set of blocks allocated as a write buffer and a second set of blocks, wherein the first set of blocks has a lower latency than the second set of blocks; and
a controller configured to:
store the data in the write buffer;
receive, from the host, a command to flush the write buffer to the second set of blocks in the memory;
determine whether the data is to be retained in the write buffer despite the command to flush the write buffer; and
in response to determining that the data is to be retained in the write buffer, retain the data in the write buffer despite the command to flush the write buffer.

11. The storage system of claim 10 , wherein the controller is further configured to receive, from the host, a command to flush the data retained in the write buffer.

12. The storage system of claim 10 , wherein the controller is further configured to receive, from the host, information indicating that the data is to be retained in the write buffer.

13. The storage system of claim 12 , wherein the information indicates one of a plurality of different retention levels.

14. The storage system of claim 12 , wherein the information comprises a dedicated command.

15. The storage system of claim 10 , wherein the controller is further configured to receive, from the host, a maximum size of the write buffer.

16. The storage system of claim 10 , wherein the first set of blocks comprises single-level cell (SLC) blocks and the second set of blocks comprises multi-level cell (MLC) blocks.

17. The storage system of claim 10 , wherein the first set of blocks comprises XPOINT memory.

18. The storage system of claim 17 , wherein the second set of blocks comprises flash memory.

19. The storage system of claim 10 , wherein the memory comprises a three-dimensional memory.

20. A storage system comprising:
a memory comprising a first set of blocks allocated as a write buffer and a second set of blocks, wherein the first set of blocks has a lower latency than the second set of blocks;
means for receiving, from a host, data to be stored in the memory;
means for storing the data in the write buffer;
means for receiving, from the host, a command to flush the write buffer to the second set of blocks in the memory;
means for determining whether the data is to be retained in the write buffer despite the command to flush the write buffer; and
means for retaining the data in the write buffer despite the command to flush the write buffer in response to determining that the data is to be retained in the write buffer.

Assignees

• Western Digital Tech Inc

Inventors

• Sela Rotem
• Zilberstein Einav
• Inbar Karin

Classifications

• G11C2207/2236

  Copy · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title