Packet-based digital display interface

US11675406B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11675406-B2
Application numberUS-202217567742-A
CountryUS
Kind codeB2
Filing dateJan 3, 2022
Priority dateFeb 3, 2010
Publication dateJun 13, 2023
Grant dateJun 13, 2023

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A passive cable adaptor for connecting a data source device with a display device is described. The adaptor has a packet-based interface connector at one end, the connector having a positive main link pin, a negative main link pin, a positive auxiliary channel pin, and a negative auxiliary channel pin. At the other end is a micro serial interface connector, wherein multimedia content is transmitted over the cable adaptor and electrical power is supplied over the cable adaptor simultaneously. The cable adaptor has an auxiliary and hot plug detect (HPD) controller utilized to map the auxiliary channel and HPD signals of the packet-based digital display to the micro serial interface ID signal.

First claim

Opening claim text (preview).

The invention claimed is: 1. A device, comprising: an enhanced serial interface receiver connector; and circuitry coupled to the enhanced serial interface receiver connector, wherein the circuitry, in operation: determines whether the enhanced serial interface receiver connector is coupled to a display device supporting serial interface downstream capability; and simultaneously transmits multimedia content via the enhanced serial interface receiver connector and receives power via the enhanced serial interface receiver connector, wherein, in response to determining the enhanced serial interface connector is coupled to a display device supporting serial downstream capability, the circuitry, in operation, receives power via a Vbus pin of a serial interface of the enhanced serial interface receiver connector and via a packet-based interface power pin of the enhanced serial interface receiver connector. 2. The device of claim 1 , wherein the circuitry, in operation, in response to determining the enhanced serial interface connector is coupled to a display device not supporting serial downstream capability, receives power via the packet-based interface power pin of the enhanced serial interface receiver connector without receiving power via the Vbus pin of the serial interface of the enhanced serial interface receiver connector. 3. The device of claim 1 , wherein the circuitry, in operation, transmits high-speed multimedia content signals. 4. The device of claim 1 , wherein the circuitry comprises data processing circuitry, which, in operation, generates the multimedia content. 5. The device of claim 1 , wherein the circuitry, in operation, determines whether the enhanced serial interface connector is coupled to an enhanced serial interface host, and sets a power level of power received via the packet-based interface power pin of the enhanced serial interface receiver connector. 6. A device, comprising: a display; a packet-based interface source receiver connector; a serial interface source receiver connector; and circuitry coupled to the display, to the packet-based interface source receiver connector and to the serial interface source receiver connector, wherein the circuitry, in operation: determines a power level to supply via the packet-based interface source receiver connector and the serial interface source receiver connector; and simultaneously receives multimedia content via the enhanced serial interface receiver connector and provides power at the determined power level via a power pin of the packet-based interface source receiver connector and via a Vbus pin of the serial interface source receiver connector. 7. The device of claim 6 , wherein the circuitry, in operation, receives high-speed multimedia content signals. 8. The device of claim 6 , wherein the circuitry comprises data processing circuitry, which, in operation, drives the display based on the received multimedia content. 9. A system, comprising: a source device having circuitry and an enhanced serial interface receiver connector coupled to the circuitry; and a cable having an enhanced serial interface plug connector, a packet-based interface source plug connector and a serial interface plug connector, wherein the enhanced serial interface plug connector of the cable, in operation, couples to the serial interface receiver connector, and the circuitry of the source device, in operation, determines whether the cable couples the serial interface receiver connector to a display device supporting serial interface downstream capability; and simultaneously transmits multimedia content and receives power via the enhanced serial interface receiver connector and the cable, wherein, in response to determining the cable couples the serial interface receiver connector to a display device supporting serial interface downstream capability, the circuitry, in operation, receives power via a Vbus pin of the serial interface plug connector of the cable and via a power pin of the packet-based interface source plug connector of the cable. 10. The system of claim 9 , wherein the circuitry, in operation, in response to determining the cable couples the serial interface receiver connector to a display device not supporting serial interface downstream capability, receives power via the power pin of the packet-based interface source plug connector of the cable, without receiving power via the Vbus pin of the serial interface plug connector of the cable. 11. The system of claim 9 , wherein the circuitry, in operation, transmits high-speed multimedia content signals via the cable. 12. The system of claim 9 , wherein the circuitry comprises data processing circuitry, which, in operation, generates the multimedia content. 13. The system of claim 9 , wherein the circuitry, in operation, determines whether the cable is coupled to an enhanced serial interface host, and sets a power level of power received via the Vbus pin of the enhanced serial interface plug connector of the cable based on the determination of whether the cable is coupled to an enhanced serial interface host. 14. The system of claim 9 , comprising: a display having a packet-based interface source receiver connector, which, in operation, couples to the packet-based interface source plug connector of the cable. 15. The system of claim 14 , wherein the display comprises: a serial interface source receiver connector, which, in operation, couples to the serial interface plug connector of the cable.

Assignees

Inventors

Classifications

  • G06F1/266Primary

    Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips · CPC title

  • where the program performs an interfacing function, e.g. device driver (G06F13/105 takes precedence; contention policies within device drivers G06F9/4881; scheduling within device drivers G06F9/52) · CPC title

  • Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

  • additional display device, e.g. video projector (digital output for controlling a plurality of local displays G06F3/1423) · CPC title

  • Power management, i.e. event-based initiation of a power-saving mode · CPC title

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What does patent US11675406B2 cover?
A passive cable adaptor for connecting a data source device with a display device is described. The adaptor has a packet-based interface connector at one end, the connector having a positive main link pin, a negative main link pin, a positive auxiliary channel pin, and a negative auxiliary channel pin. At the other end is a micro serial interface connector, wherein multimedia content is transmi…
Who is the assignee on this patent?
St Microelectronics Inc
What technology area does this patent fall under?
Primary CPC classification G06F1/266. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 13 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).